Chip stack package utilizing a dummy pattern die between...

Details Chip stack package utilizing a dummy pattern die between... Chip stack package utilizing a dummy pattern die between...

2006-07-12

2009-06-23

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S774000, C257S777000, C257S780000, C257SE23011

Reexamination Certificate

active

07550835

ABSTRACT:
The chip stack package includes at least a printed circuit board having a bond finger and a ball land, and at least two semiconductor chips stacked on the printed circuit board while being spaced from each other and formed with a plurality of bonding pads. A dummy pattern die is attached to the upper surface of each semiconductor chip. The dummy pattern die is formed with a circuit pattern on its lower surface for electrical connection to the semiconductor chip. The dummy pattern is also formed with a via pattern on its upper side which is connected to the circuit pattern. The first solder balls electrically connects the bond finger with the circuit pattern while electrically connecting the via pattern of stacked dummy pattern dies with the circuit pattern. The second solder balls are attached to the ball land of the printed circuit board.

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patent: 1020010004527 (2001-01-01), None
patent: 1020060029715 (2006-04-01), None

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