Chip stack package and manufacturing method thereof

Details Chip stack package and manufacturing method thereof Chip stack package and manufacturing method thereof

2007-10-02

2007-10-02

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S774000

Reexamination Certificate

active

10890995

ABSTRACT:
A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

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Korean Office Action dated Jun. 29, 2005 received in Korean Appl. No. 10-2003-0059166.

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