Chip sizing for hierarchical designs

Details Chip sizing for hierarchical designs Chip sizing for hierarchical designs

1996-04-23

1998-03-24

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750

Patent

active

057319855

ABSTRACT:
A method for resizing the macro cells' boundaries of an integrated chip is disclosed and that becomes effectual after the initial floorplanning process has been completed. The method of the present invention apportions any excess area that is freed-up after the initial floorplanning process by altering the sizes or dimensions of the macro cell within the hierarchy of the integrated circuit in such a manner that the fractional change in the percentage occupancy is substantially constant among all macro cells at all hierarchy levels.

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A. R. Bruss, et al., "Flexible Image for Physical Layout of Circuits", IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, pp. 6687-6691.

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