Chip-sized semiconductor device and process for making same

Details Chip-sized semiconductor device and process for making same Chip-sized semiconductor device and process for making same

1999-07-06

2001-07-03

Gandhi, Jayprakash N. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S765000, C361S772000, C361S777000, C361S783000, C361S807000, C174S255000, C174S260000, C174S262000, C174S266000, C257S737000, C257S786000, C257S783000, C257S738000

Reexamination Certificate

active

06256207

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device having substantially the same size as a semiconductor element or chip itself, hereinafter referred to as “chip-sized semiconductor device or package” and a process for making the same.
2. Description of the Related Art
A chip-sized package is a semiconductor device which has a substantially the same size as a semiconductor chip itself, in which a mounting substrate has a substantially the same size as a semiconductor chip and has external connecting terminals, such as solder balls, on a mounting surface thereof so that a semiconductor chip can be mounted on the mounting substrate by means of the external connecting terminals. Usually, the chip-sized package is a multi-pin type in which the external connecting terminals are arranged in a array on the mounting surface thereof.
FIG. 5
shows an example in which the lands
14
for connecting the external connecting terminals are arranged on the mounting surface of the semiconductor element
10
. The semiconductor element
10
has electrodes
12
on the surface thereof. Wiring patterns
16
connect the electrodes
12
to the lands
14
, respectively.
One example of methods for arranging the lands
14
on an electrode forming surface of the semiconductor element
10
is that, wiring patterns
16
are first formed on a passivation film of a semiconductor element
10
and then lands
14
are formed at the tip ends of the wiring patterns
16
. Another example is that a wiring pattern film, used as an interposer, is first arranged on the electrode forming surface of the semiconductor element
10
and wiring patterns are then formed on the film to connect the lands
14
to the lands
14
and to the electrodes
12
, so that the electrodes
12
are electrically connected to the lands
14
, respectively.
In any case, it is necessary that the land, which is connected to the external connecting terminal, has a diameter of about 300 &mgr;m. Therefore, if the lands
14
are arranged by themselves on the electrode forming surface of the semiconductor element
10
, the spaces between the adjacent lands
14
will be very narrow and therefore the space for arranging the wiring patterns
16
are restricted. If the electrodes
12
are densely arranged and the number of pins is increased, the number of wiring patterns for connecting mutually between the electrodes and the lands will be increased and it will become difficult to preserve the enough spaces for arranging the wiring patterns
16
.
If the wiring patterns
16
cannot be arranged on the electrode forming surface of the semiconductor element
10
, a multi-layer structure of wiring patterns
16
must be used. However, such a multi-layer structure will make it difficult and complicated to produce the semiconductor devices, thereby reducing the reliability thereof.
Even if a wiring pattern film is arranged, as an interposer, to electrically connect the lands
14
to the electrodes
12
of the semiconductor element
10
, forming such a wiring pattern film is complicated and also a connecting operation between the lands
14
and the electrodes
12
will be complicated and troublesome.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a chip-sized semiconductor device or package and a process for making the same, in which a multi-pin structure of such a package with a simple construction can easily be obtained and such a package can easily be made with a low cost.
According to the present invention, there is provided a chip-sized semiconductor device comprising: a semiconductor element having a plurality of electrodes and a plurality of connecting pads electrically connected to the respective electrodes; a connecting board comprising a base substrate having a first surface and a second surface, a plurality of connecting holes extending from the first surface to the second surface, a plurality of lands formed on the first surface to close the respective connecting holes, the lands being arranged in conformity with positions of the connecting pads of the semiconductor element, each of the connecting pads having a surface area smaller than that of the land; the semiconductor element being mounted on the connecting board in such a manner that the connecting pads of the semiconductor element are electrically connected to the respective lands of the connecting boards by means of a plurality of bumps, respectively; and a plurality of external connecting terminals on the second surface of the base substrate to be in contact with the respective lands through the respective connectings holes.
A plurality of wiring patterns are provided on an electrode forming surface of the semiconductor element to electrically connect the respective electrodes to the respective connecting pads.
The base substrate is made of an electrically insulating material, such as resin, and the first surface of the base substrate is covered with an electrically insulating protective film in such a manner that a part of the respective land is exposed to define a contact portion, to which the respective bump is to be adhered, the contact portion having a surface area smaller than that of the land.
A gap defined between the semiconductor element and the connecting board is filled with an electrically insulating underfill.
According to another aspect of the present invention, there is provided a chip-sized semiconductor device comprising: a semiconductor element having a plurality of electrodes and a plurality of connecting pads electrically connected to the respective electrodes; a connecting board comprising a base substrate having a first surface and a second surface, a plurality of connecting holes extending from the first surface to the second surface, a plurality of lands formed on the first surface to close the respective connecting holes, the lands being arranged in conformity with positions of the connecting pads of the semiconductor element, each of the connecting pads having a surface area smaller than that of the land; and the semiconductor element being mounted on the connecting board in such a manner that the connecting pads of the semiconductor element are electrically connected to the respective lands of the connecting board by means of a plurality of bumps, respectively.
According to a further aspect of the present invention, there is provided a package for mounting thereon a semiconductor element, the package comprising: a connecting board comprising a base substrate having a first surface and a second surface, a plurality of connecting holes extending from the first surface to the second surface, a plurality of lands formed on the first surface to close the respective connecting holes, the lands being arranged in conformity with positions of connecting pads of a semiconductor element which is to be mounted on the connecting board, each of the lands having a surface area larger than that of the connecting pads; and a plurality of external connecting terminals on the second surface of the base substrate to be in contact with the respective lands through the respective connectings holes.
According to still further aspect of the present invention, there is provided a process for making a chip-sized semiconductor device, the process comprising the steps of: preparing a connecting board comprising a base substrate having a first surface and a second surface, a plurality of connecting holes extending from the first surface to the second surface, a plurality of lands formed on the first surface to close the respective connecting holes, the lands being arranged in conformity with positions of connecting pads of a semiconductor element which is to be mounted on the connecting board, each of the lands having a surface area larger than that of the connecting pads; mounting the semiconductor on the connecting board in such a manner that the connecting pads of the semiconductor element are electrically connected to the respective lands of the connecting board by m

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