Chip size semiconductor packages with stacked dies

Details Chip size semiconductor packages with stacked dies Chip size semiconductor packages with stacked dies

2000-09-05

2003-06-10

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S618000, C257S620000, C257S621000, C257S686000, C438S460000, C438S461000, C438S462000

Reexamination Certificate

active

06577013

ABSTRACT:

BACKGROUND
1. Technical Field
This invention pertains to semiconductor packaging in general, and in particular, to making chip size semiconductor packages (“CSPs”) having stacked dies and requiring no interconnective substrate.
2. Related Art
The increasing demand for electronic devices that are smaller, lighter, and yet more functional has resulted in the development of so-called chip-size semiconductor packages (“CSPs”) having outline and mounting (“O&M”) dimensions that are only slightly larger than those of the semiconductor die, or “chip,” packaged therein. Another result has been the development of techniques for stacking two or more semiconductor dies on top of one another within the package. Examples of die-stacking techniques may be found, for example, in U.S. Pat. No. 5,682,062 to S. J. Gaul; U.S. Pat. No. 5,323,060 to R. Fogel, et al.; U.S. Pat. No. 5,815,372 to W. N. Gallas; U.S. Pat. No. Re. 36,613 to M. B. Ball; U.S. Pat. No. 5,721,452 to R. Fogel, et al.; and, Japanese Patent Disclosures 62-126661, 4-56262, 63-128736, and 10-256470.
FIG. 1
is a cross-sectional side elevation view of a conventional ball grid array (“BGA”) type of package
110
. The package
110
includes two stacked dies
114
and
116
mounted on a substrate
112
. The connective substrate
112
illustrated comprises a layer
120
of an insulative material, e.g., a polyimide resin film, laminated between top and bottom conductive layers
122
,
124
of a metal, e.g., copper or aluminum, that have been patterned using conventional photo-etching techniques.
A plurality of bonded wires
138
electrically connect bonding pads
134
on the peripheries of the respective dies
114
,
116
to bonding pads in the top conductive layer
122
of the substrate
112
. Vias
132
, i.e., plated-through holes, electrically connect the top conductive layer
122
to the bottom conductive layer
124
. Input-output (“I-O”) terminal balls
118
are mounted on the bottom conductive layer
124
. Accordingly, the dies
114
,
116
are electrically connected to the balls
118
. The bottom die
114
is attached to the top surface of the substrate
112
with an adhesive layer
136
. The top die
116
is attached to, and vertically spaced from, the bottom die
114
by another adhesive layer
140
. An insulative plastic mold cap
144
protectively encapsulates the dies
114
,
116
, wire bonds
138
, and the top surface of the substrate
112
.
Other types of packages having stacked dies include a metal leadframe instead of an insulative substrate. See, e.g., U.S. Pat. No. Re. 36,613, above.
It may be seen in each of the stacked-die packages described above, including the stacked-die CSP
110
illustrated in
FIG. 1
, that a large portion of the size, complexity, and hence, expense, of the package is associated with the inter-connective substrate
112
and the connections of the dies
114
and
116
to it. It would therefore be desirable if the cost, complexity and size added to the package by the substrate
112
could be reduced or eliminated. It would further be desirable if the molding operation used to form the mold cap
144
could also be eliminated.
BRIEF SUMMARY
This invention provides a method for making chip-size semiconductor packages (“CSPs”) with stacked dies that eliminates the expense, complexity, and added size of an interconnective substrate, such as a laminate or a lead frame, in the package, as well as the molding operation conventionally used to encapsulate the dies in a protective plastic body.
One embodiment of the method includes the provision of a semiconductor wafer having a plurality of semiconductor dies formed integrally therein. Each die has opposite first and second surfaces and an electronic integrated circuit (“IC”) device formed in the first surface thereof. One or more conventional wire bonding terminal pads are located on the first surface of each die around its periphery and are electrically connected to the electronic device in the die internally thereof.
A via having walls with an insulative coating thereon is formed through the dies and each terminal pad thereon. The vias are burned through the dies and terminal pads with a laser, and in one embodiment, at a temperature high enough to form the insulative coating on the walls of the vias simultaneously with their formation. The walls of the vias can be tapered to facilitate the insertion of pins into them, and can be plated with an electrically conductive material to facilitate electrical connection of the pins to the dies. When processing of the wafer is complete, the dies are “singulated,” i.e., separated, from the wafer, e.g., by sawing.
Two or more of the singulated dies are then stacked on top of one another and electrically connected to form a CSP with stacked dies. In one embodiment, the vias in each die of the stack are slid, one die at a time, over the ends of a corresponding plurality of electrically conductive pins held in a fixture, until the desired number of dies in the stack has been obtained, and the pins are then soldered to corresponding ones of the terminal pads on the respective dies. In another embodiment, the dies are held stacked on top of one another in a fixture such that corresponding vias in each die are held in coaxial alignment with each other. An electrically conductive pin is then inserted through each set of aligned vias and soldered to corresponding ones of the terminal pads on the respective dies.
In one embodiment, a portion of each conductive pin protrudes below the first; or bottommost, die in the stack and comprises an input-output terminal of the package. In another embodiment, heat spreaders are interleaved between the dies to conduct heat away from the dies and to the surrounding ambient.
A better understanding of the above and other features and advantages of the invention may be had from a consideration of the detailed description below of some exemplary embodiments thereof, particularly if such consideration is made in conjunction with the appended drawings.


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