Chip-size semiconductor package

Details Chip-size semiconductor package Chip-size semiconductor package

2006-01-17

2006-01-17

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S773000, C257S784000, C257S786000, C257S737000, C257S738000, C257S780000, C257S690000, C257S787000

Reexamination Certificate

active

06987323

ABSTRACT:
A chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a conductive wiring pattern electrically connected to the metal pad; a molding resin formed over the conductive wiring pattern; and a terminal member which is electrically connected to the conductive wiring pattern, wherein the conductive wiring pattern comprises a termial portion on which the terminal member is formed, an extended portion extending from the terminal portion and a connecting portion arranged between the terminal portion and the extended portion. The portion connecting portion between the extended portion and the terminal portion is provided with a slit, to disperse stress applied to the connecting portion.

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patent: 6313541 (2001-11-01), Chan et al.
patent: 6417575 (2002-07-01), Harada et al.
patent: 402049429 (1990-02-01), None
patent: 2000-183214 (2000-06-01), None

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