Chip-size semiconductor package

Details Chip-size semiconductor package Chip-size semiconductor package

1997-06-17

1999-11-02

Williams, Alexander O.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

257786, 257698, 257696, 257781, H01L 2348, H01L 2358, H01L 23495

Patent

active

059776439

ABSTRACT:
A chip-size semiconductor package and fabrication method is provided that reduces the size of the package. Further, the electrical path from the chip pads to the external leads is reduced to improve electrical characteristics. In addition, the external leads can be formed directly at the location of the chip pads. The chip-size semiconductor package has a passivation film is formed on a semiconductor chip excluding the chip pads thereon. Inner ends of conductive wires are vertically coupled to corresponding chip pads, respectively. Then, the semiconductor chip is sealed with a molding resin excluding the outer ends of the conductive wires that protrude. The outer ends can be formed as external leads having a shape, such as circular external balls, based on the intended use.

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"Semicon Japan '94 Symposium", Mitsubishi Electric, Dec. 23, 1994.

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