Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
1999-06-23
2001-04-03
Kincaid, Kristine (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S778000, C257S779000, C257S780000, C257S687000
Reexamination Certificate
active
06211461
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip size package and method of fabricating the same, more particularly to a chip size package having a plurality of solder balls arranged in array and method of fabricating the same.
2. Description of the Related Art
There are various types of semiconductor packages, such as, a small outline J-lead type(hereinafter “SOJ”) for general use, a zigzag inline package type(hereinafter “ZIP”) for particular occasion and a thin small outline package type (hereinafter “TSOP”) for memory card which has been standardized.
Hereinafter, a method for manufacturing the above semiconductor package will be described.
In a sawing step, a wafer is cut along a scribe line thereby separating the wafer into individual semiconductor chips, and then a die attaching step is followed so that a lead frame is attached to each semiconductor chip.
Next, the semiconductor chip is cured at a given temperature and for a given amount of time. A wire bonding step is performed so as to electrically connect a bonding pad of the semiconductor chip and an inner lead of the lead frame by means of a metal wire.
After the wire bonding step, the semiconductor chip is molded with an epoxy compound (i.e. a molding step). By doing so, the semiconductor chip is protected from thermal or mechanical impacts originated from outer circumstances.
Afterward, an outer lead of the lead frame is plated (i.e. a plating step), and a dam bar supporting the outer lead is cut (i.e. a trimming step) and successively the outer lead is formed in a selected shape capable of easy mounting to a substrate (i.e. a forming step).
Most recently, a chip size package having approximately the same size of semiconductor chip has been developed instead of the above package manufactured according to foregoing procedure. The chip size package uses a Tape Automated Bonding (hereinafter “TAB”) tape instead of the lead frame which is typically used in common package, and a plurality of solder balls arranged in array for mounting to a substrate.
In a conventional chip size package as shown in
FIG. 1
, a bump
2
is formed on a bonding pad of a semiconductor chip
1
. A TAB tape
3
in which a metal pattern made of copper is formed, is attached to the bump
2
by thermal pressure and is electrically connected thereto. A resultant structure is completely molded with an epoxy compound
4
, and then a solder ball is mounted on a ball land disposed on a lower portion of the TAB tape
3
.
The conventional chip size package as constituted above, however, is required to improve its thickness-oriented drawback since the thickness of the TAB tape
3
including the epoxy compound
4
increases total thickness of the package while the trend in the package industry is to minimize its size.
There is a crack in the bump
2
or in the TAB tape
3
, the crack is caused by a mechanical impact raised when the bump
2
and the TAB tape
3
are thermally pressed.
There is also generated a metal compound at a contact surface between the ball land and solder balls
5
.
Especially, the TAB tape
3
, itself includes remaining ions or moisture and there might be a malfunction in a package operation frequently. Furthermore, a short owing to a damage in an insulating film which insulates the metal pattern in the TAB tape
3
, is occurred. Also, the TAB tape
3
is expected to redesign according to the changes in location and pitch of pads and solder balls.
SUMMARY OF THE INVENTION
It is one object of the present invention to solve the foregoing problems by providing a chip size package having an innovative package structure capable of minimizing thickness thereof where the thickness of chip size package is identical with that of a semiconductor chip, and by providing a method of manufacturing the same.
It is another object of the present invention to prevent destruction of bonding pads due to a mechanical impact by substituting metal wires instead of bumps.
It is a further object of the present invention to prevent chemical reaction between solder balls and a ball land by modifying the process of attaching solder balls.
It is an additional object of the present invention to prevent various other problems owing to a TAB tape by disusing the TAB tape.
So as to accomplish forgoing objects of the present invention, a chip size package according to this invention is constituted as follows.
In one embodiment, a recess is formed in an upper portion of a semiconductor chip, and bonding pads are formed at a bottom center of the recess. A lower end of a metal wires is connected to the bonding pads. The recess is filled with an epoxy compound, herein an upper end of the metal wires is protruded from the epoxy compound. Bumps are formed on the protruded upper end of the metal wire. Solder balls are mounted on the bumps.
Three methods of manufacturing the chip size package as constituted above are given below.
In one aspect, recesses are formed in a surface of an initial to wafer. Integrated circuits are formed on bottoms of the respective recesses thereby constituting a semiconductor chip, and then passivation layers are deposited on the bottoms of the respective recesses. Next, a pair of bonding pads and a pair of insulating pads are formed on the bottoms of the respective recesses. The bonding pads and the insulating pads are electrically connected with metal wires, herein a midway portion of the metal wires is protruded from the surface of the wafer. The recesses are filled with an epoxy compound such that the midway portion of the metal wire is exposed from the epoxy compound. Afterward, the wafer is cut off and separated into individual semiconductor chips. Bumps are formed on the midway portions of the metal wires being exposed from the epoxy compound, and solder balls are mounted on the bumps.
In another aspect, recesses are formed in a surface of an initial wafer. Integrated circuits are formed on bottoms of the respective recesses thereby constituting a semiconductor chip, and then passivation layers are deposited on the bottoms of the respective recesses. Next, bonding pads are formed on the bottoms of the respective recesses, and dummy pads are formed on the surface of the wafer. The bonding pads and the dummy pads are electrically connected with metal wires. The recesses are filled with an epoxy compound. A surface of the epoxy compound is polished thereby removing the dummy pads and simultaneously exposing the metal wires from the epoxy compound. Bumps are formed on the metal wires being exposed from the epoxy compound. Afterward, the wafer is cut off and separated into individual semiconductor chips. Solder balls are mounted on the bumps.
In a further aspect, recesses are formed in a surface of an initial wafer. Integrated circuits are formed on bottoms of the respective recesses thereby constituting a semiconductor chip, and then passivation layers are deposited on the bottoms of the respective recesses. Next, bonding pads are formed on the bottoms of the respective recesses. Each bonding pad formed in a recess is electrically connected to the other bonding pad formed in another recess adjacent to said recess with a metal wire. The recesses are filled with an epoxy compound. The wafer is cut off and separated into individual semiconductor chips thereby cutting midway portions of the metal wires. A surface of the epoxy compound is polished thereby exposing the cut midway portions of the metal wires from the epoxy compound. Bumps are formed on the midway portions of the metal wires being exposed from the epoxy compound. Solder balls are mounted on the bumps.
In another embodiment being different from the first embodiment, bonding pads and insulating pads are formed on a surface of a semiconductor chip. The bonding pads and the insulating pads are electrically connected to each other with metal wires. A cap made of ceramic in which a withdrawing slot is formed, is installed on the semiconductor chip. Midway portions of the metal wires are exposed through the withdrawing slot. Bumps are formed o
Kim Ji Yon
Park Sang Wook
Hyundai Electronics Industries Co,. Ltd.
Kincaid Kristine
Ladas & Parry
Ngo Hung V
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