Chip size package

Details Chip size package Chip size package

1997-08-18

1999-06-01

Kincaid, Kristine

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

361783, H01L 2500

Patent

active

059090103

ABSTRACT:
A CSP (Chip Size Package) of the present invention includes a semiconductor IC (Integrated Circuit) chip having I/O (Input/Output) terminals along its edges. A small size substrate has a smaller contour than the chip and has a plurality of metal terminals arranged along the edges of its bottom, and a plurality of metal bumps arranged on its top in a lattice configuration. The top of the chip and the bottom of the substrate are so configured as to be electrically connected to each other via a tape member including a plurality of leads. These leads each include a first terminal to be electrically connected to the associated I/O terminal of the chip, and a second terminal to be electrically connected to the associated metal terminal of the substrate.

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