Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2000-06-07
2002-11-05
Enad, Elvin (Department: 2832)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S774000, C257S784000, C257S734000
Reexamination Certificate
active
06476482
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit packages and more specifically to chip-size package (CSP) structures.
2. Description of the Related Art
In a prior art CSP structure, shown in
FIGS. 1 and 2
, a copper wire
12
is patterned on the base
14
a
of a polyimide tape
14
b
and partially covered with edges of the tape
14
b
. Copper wire
12
has a portion having a greater width than the rest. Base
14
a
is perforated by a laser beam to create a hole beneath the copper wire
12
and the hole is then electroplated to form a copper bump
11
that extends below the wider section of the copper wire
12
. These elements are the upper structure of the chip-size package and constitute what is known as an interposer tape for interconnecting external circuitry and an integrated circuit which forms the lower structure of the chip-size package. The bottom surface of the copper bump
11
has a gold-plated layer
16
. A chip-size packet is formed when the polyimide base
14
a
is secured by an adhesive layer
15
to a silicon substrate
18
of an integrated circuit chip and the gold-plated layer
16
is brought into contact with an aluminum pad
17
of the integrated circuit chip. A gold-aluminum contact is thus established between the copper bump
11
and the substrate
18
by application of heat and pressure so that the integrated circuit chip has access to external circuitry. Since silicon and polyimide have different values of thermal expansion coefficient, the application of heat produces a mechanical stress that causes the aluminum pad to be misaligned with the copper bump
11
as indicated by a dotted line
17
′. This is undesirable from the viewpoint of product yield and reliability.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a chip-size package structure of high reliability that can be manufactured at high yield and a method of fabricating the chip-size package structure.
According to a first aspect of the present invention, there is provided a chip-size package comprising an insulator tape formed with a conductive wire having a wider section which is greater in width than other sections of the wire and a conductive bump connected to the wider section of the wire, the tape being formed with a first plurality of slits arranged on one side of the wider section and a second plurality of slits arranged on the other side of the wider section. An integrated circuit chip is provided having a conductive pad connected to the copper bump.
According to a second aspect, the present invention provides a method of fabricating a chip-size package comprising the steps of forming a conductive wire on an insulator tape, the wire having a wider section which is greater in width than other sections of the wire and a conductive bump connected to the wider section of the wire, forming, in the insulator tape, a first plurality of slits arranged on one side of the wider section and a second plurality of slits arranged on the other side of the wider section, securing the insulator tape to an integrated circuit chip having a conductive pad thereon, and pressure contacting the copper bump to the conductive pad while applying heat thereto.
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Matsumoto Yoshihiro
Okazaki Shohei
Enad Elvin
Lee Kyung S.
LandOfFree
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