Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2007-01-30
2007-01-30
Chambliss, Alonzo (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S786000, C326S041000
Reexamination Certificate
active
10134764
ABSTRACT:
A chip generally comprising a logic circuit and a plurality of pads. The logic circuit may be configured to operate in a plurality of modes in response to a mode signal. The pads may be configurable into a plurality of subsets such that one of the subsets is used by the logic circuit at a time in response to the mode signal.
REFERENCES:
patent: 5181201 (1993-01-01), Schauss et al.
patent: 5796266 (1998-08-01), Wright et al.
patent: 5872737 (1999-02-01), Tsuruda et al.
patent: 5991232 (1999-11-01), Matsumura et al.
patent: 6038188 (2000-03-01), Akamatsu
patent: 6180426 (2001-01-01), Lin
patent: 6242737 (2001-06-01), Ohnishi et al.
patent: 6353333 (2002-03-01), Curd et al.
patent: 6586266 (2003-07-01), Lin
patent: 6597602 (2003-07-01), Imamiya et al.
Chambliss Alonzo
Cypress Semiconductor Corp.
Maiorana PC Christopher P.
LandOfFree
Chip select method through double bonding does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Chip select method through double bonding, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip select method through double bonding will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3781541