Chip scale surface mounted device and process of manufacture

Details Chip scale surface mounted device and process of manufacture Chip scale surface mounted device and process of manufacture

2006-10-17

2006-10-17

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S693000

Reexamination Certificate

active

07122887

ABSTRACT:
A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

REFERENCES:
patent: 3561107 (1971-02-01), Best et al.
patent: 3871014 (1975-03-01), King et al.
patent: 3972062 (1976-07-01), Hopp
patent: 4021838 (1977-05-01), Warwick
patent: 4604644 (1986-08-01), Beckham et al.
patent: 5047833 (1991-09-01), Gould
patent: 5217922 (1993-06-01), Akasaki et al.
patent: 5311402 (1994-05-01), Kobayashi et al.
patent: 5313366 (1994-05-01), Gaudenzi et al.
patent: 5367435 (1994-11-01), Andros et al.
patent: 5371404 (1994-12-01), Juskey et al.
patent: 5381039 (1995-01-01), Morrison
patent: 5394490 (1995-02-01), Kato et al.
patent: 5397921 (1995-03-01), Karnezos
patent: 5447886 (1995-09-01), Rai
patent: 5448114 (1995-09-01), Kondoh et al.
patent: 5451544 (1995-09-01), Gould
patent: 5454160 (1995-10-01), Nickel
patent: 5477087 (1995-12-01), Kawakita et al.
patent: 5510758 (1996-04-01), Fujita et al.
patent: 5512786 (1996-04-01), Imamura et al.
patent: 5532512 (1996-07-01), Fillion et al.
patent: 5554887 (1996-09-01), Sawai et al.
patent: 5578869 (1996-11-01), Hoffman et al.
patent: 5654590 (1997-08-01), Kuramochi
patent: 5703405 (1997-12-01), Zeber
patent: 5726489 (1998-03-01), Matsuda et al.
patent: 5726501 (1998-03-01), Matsubara
patent: 5726502 (1998-03-01), Beddingfield
patent: 5729440 (1998-03-01), Jimarez et al.
patent: 5734201 (1998-03-01), Djennas et al.
patent: 5739585 (1998-04-01), Akram et al.
patent: 5814884 (1998-09-01), Davis et al.
patent: 5814894 (1998-09-01), Igarashi et al.
patent: 5904499 (1999-05-01), Pace
patent: 6133634 (2000-10-01), Joshi
patent: 6391687 (2002-05-01), Cabahug et al.
patent: 6744124 (2004-06-01), Chang et al.
patent: 6774466 (2004-08-01), Kajiwara et al.
patent: 5-129516 (1993-05-01), None
patent: 07-202064 (1995-04-01), None
patent: 11-054673 (1999-02-01), None
patent: 2000-243887 (2000-08-01), None
MOSFET BGA Design Guide 2004-Fairchild Semiconductor, pp. i-ii and pp. 1-43.

Affiliated with

Also associated with

Rating

Chip scale surface mounted device and process of manufacture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip scale surface mounted device and process of manufacture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip scale surface mounted device and process of manufacture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3719137