Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-09-22
2002-12-10
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S758000, C438S108000
Reexamination Certificate
active
06492726
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and, more particularly, to a method and package for a multi-chip module which employs stacked dies.
(2) Description of the Prior Art
Semiconductor devices have over the years been increasingly denser packaged, placing increased demands on such device package considerations as heat dissipation and input/output (I/O) capability. These increased demands have led to new device packaging concepts and approaches where, for many of these approaches, more than one device is packaged per individual packaging unit. From this has been developed a family of Chip Scale Packages (CSP) that is aimed at satisfying demands of miniaturization and multi-function capabilities by means of a high I/O count. CSP packaging techniques are still relatively expensive, requiring sophisticated and expensive equipment since they include the packaging of devices in packages that are substantially of equal size or slightly larger than the original device. The main objective for the introduction of CSP packages is the reduction in the size of the overall package. The package is designed to redistribute very fine pitch wiring from the perimeter of the die to the perimeter of the substrate carrier. CSP packages are also easy to use for burn-in of previously known good devices and are easy to test. In addition, CSP packages offer a number of advantages that relate to the manufacturing of the package such as ease of handling, assembling and rework, easy to standardize and are relatively free of internal stresses that at times can lead to device damage.
To further extend the packaging of individual devices, packages have been developed wherein more than one device can be packaged at one time on a lead frame strip. The lead frame strip not only provides mechanical support for the device but in addition provides one or more layers of interconnect lines that enable the device to be connected to surrounding circuitry, relieving I/O count requirements. Of importance to and driving most of the more complicated packaging designs are considerations of I/O count (contact ball pitch), heat dissipation, matching of thermal expansion between a mother board and host components, cost of manufacturing, ease of integration into an automated manufacturing facility, package reliability and easy adaptability of the package to additional packaging interfaces such as a Printed Circuit Board (PCB). A PCB is one of the Chip-On-Board (COB) techniques that are used to attach semiconductor die to a printed circuit board. COB techniques include flip chip attachment, wirebonding, and tape automated bonding (TAB). Flip chip attachment consists of attaching a flip chip to a printed circuit board or to another substrate. A flip chip is a semiconductor chip that has a pattern or arrays of terminals spaced around an active surface of the flip chip for face-down mounting of the flip chip to a substrate. Generally, the flip chip active surface has one of the following electrical connectors: Ball Grid Array (BGA, wherein an array of minute solder balls is disposed on the surface of the flip chip that attaches to the substrate); Slightly Larger than Integrated Circuit Carrier (SLICC) (which is similar to the BGA but has a smaller solder ball pitch and diameter than the BGA); a Pin Grid Array (PGA) (wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto). With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror image of the connecting bond pads on the printed circuit board so that precise connection can be made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror image of the recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place.
Glob top and underfill materials are often used to hermetically seal the flip chips on the substrate. An underfill encapsulant is generally disposed between the semiconductor chip and the printed circuit board or substrate for environmental protection and to enhance the attachment of the semiconductor die to the substrate. In certain applications, only an underfill encapsulant is used in the semiconductor assembly without protecting the back surface of the semiconductor chip. The exposure of the semiconductor chip back surface leaves the semiconductor chip susceptible to damage. Furthermore, the application of the underfill encapsulant must be closely monitored. For example, too little underfill does not protect the device sufficiently enough from outside contaminants and can give rise to a greater concentration of voids. Such voids can lead to catastrophic failure of the chip. If too much underfill is used, the underfill encapsulant can rise to cover the edges of the chip and can expand or spread out to adjacent areas of the board that do not require fill. Since the underfill encapsulant does not protect the back of the chip, an additional protective step of providing a glob top is typically used. The technique of applying the underfill encapsulant comprises dispensing the underfill encapsulant in a liquid form and allowing capillary action to draw the underfill between the die and the substrate. The underfill then solidifies upon oven curing and reinforces all electrical connections that have been made to the die. A variety of polymers can be used as underfill encapsulants, including thermosetting molding compounds such as silicones, epoxies, polyamides and parylenes. A glob of encapsulant material is generally applied to the COB assembly to surround the semiconductor chip and the substrate. Organic materials used in the glob top encapsulation are generally selected for low moisture permeability and low thermal coefficient of expansion to avoid moisture or mechanical stress. The thermal properties are however often not optimal for removing heat efficiently away from the semiconductor die or for use in high temperature areas. Furthermore, the introduction of the glob can induce detrimental stresses that can cause catastrophic failures.
For the encapsulation of semiconductor die, organic polymeric encapsulants have mostly been used such as thermoplastic, thermoset and elastomer. Also used are hermetic seals combined with heat sinks for protection of the die from environmental and thermal damage. With the many interfaces that are used for the mounting of semiconductor devices, these interfaces provide extended networks of interconnect lines that are used to expand the fine pitch I/O points of the die to an I/O pitch that is easier to handle and more reliable.
One of the more recent approaches in semiconductor device packaging has introduced a method of vertical stacking of devices in one package. In this manner, individual devices can be mounted on for instance a bonding tape, the bonding tapes with the attached die can be stacked and are further interconnected with conductive inter-connectors that intersect with the planes of the bonding tapes.
U.S. Pat. No. 6,051,886 (Fogal et al.) shows an offset die stacking arrangement.
U.S. Pat. No. 5,744,827 (Jeong et al.) shows a three-dimensional stack package including a plurality of individual semiconductor devices.
U.S. Pat. No. 6,075,710 (Lau) discloses a package in which an Integrated Circuit chip is supported on a single core, double-layer substrate as a flip chip.
U.S. Pat. No. 6,051,887 (Hubbard) provides a stacked semiconductor device with BGA.
U.S. Pat. No. 5,951,804 (Kweon et al.) provide a method for simultaneously manufacturing chip-scale packages, employing a lead frame strip having a plurality of lead frames.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a pac
Ang Ting Cheong
Leung Ying Keung
Loong Sang Yee
Quek Shyue Fong
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Potter Roy
Saile George O.
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