Chip scale packaging with improved heat dissipation capability

Details Chip scale packaging with improved heat dissipation capability Chip scale packaging with improved heat dissipation capability

2006-04-18

2006-04-18

Quach, T. N. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257S720000, C257S738000

Reexamination Certificate

active

07030487

ABSTRACT:
A chip scale packaging with improved heat dissipation capability is disclosed. A chip or die is adhered to the first surface of a packaging substrate having a plurality of metalized through holes thereon. A functional solder ball array is implanted on the second surface of the packaging substrate. Heat-dissipating solder balls are implanted around the functional solder ball array on the second surface of the packaging substrate. The heat-dissipating solder balls are connected to the metalized through holes. The bonding pads of the chip are bonded through a central window to the corresponding bonding pads on the second surface of the packaging substrate.

REFERENCES:
patent: 6479321 (2002-11-01), Wang et al.
patent: 6563712 (2003-05-01), Akram et al.
patent: 6569712 (2003-05-01), Ho et al.
patent: 6818538 (2004-11-01), Chiang et al.

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