Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-06-08
2001-02-20
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S110000, C438S118000, C438S121000, C438S125000
Reexamination Certificate
active
06190943
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor chip packaging technology, and more particularly to a chip scale packing method.
BACKGROUND OF THE INVENTION
The so-called “chip scale package” is referred to the post-package chip module which is nearly corresponding in size to the semiconductor chip, thereby resulting in the reduction in overall volume of an electronic terminal product made of the chip module.
FIG. 1
shows a sectional schematic view of a conventional semiconductor chip module, which conforms to the requirements of the chip scale package and comprises a double-sided conductive base
10
; a semiconductor chip
12
attached to the upper surface of the base
10
by an adhesive layer
14
such that the active surface of the chip faces upward; a plurality of bonding wires
15
connecting a plurality of bonding pads (not shown in the drawing) disposed on the active surface of the chip
12
with the electrical bonding points (not shown in the drawing) which are disposed on the upper surface of the base
10
; a plurality of spherical points grid arrays
16
disposed in the underside of the base
10
; and a plastic packaging unit
18
for containing hermetically the chip
12
and the bonding wires
15
.
Such a conventional semiconductor chip module as described above is defective in design in that the double-sided base
10
must be additionally treated with the costly processes, such as drilling, electroplating, hole-filling, planarizing, etc. In addition, the total useable area of the base
10
is substantially reduced by the holes, which also adversely affect the layout of the printed circuit.
The U.S. Pat. No. 5,811,879 discloses a semiconductor chip module comprising a single-sided conductive base, which is free from the deficiencies of the double-sided conductive base described above. However, the single-sided conductive base is provided in the upper surface with a plurality of recesses in which the chips are secured in place by an adhesive. It is conceivable that the recesses undermine the structural integrity and strength of the single-sided conductive base. In addition, it is time-consuming to provide the chips with an adhesive coating. Moreover, the reliability of the semiconductor chip module is reduced by the interstices which exist between the recess and the chip in the event that the recess and the chip do not match well in size. In other words, such a prior art single-sided conductive base as described above has a high rejection rate.
SUMMARY OF THE INVENTION
It is therefore the primary objective of the present invention to provide a chip scale method for packaging a semiconductor chip module comprising a single-sided conductive base which is cost-effective and is not susceptible to damage in structural integrity as well as weakness in structural strength in the course of the packaging process.
It is another objective of the present invention to provide a chip scale packaging method for assembling a semiconductor chip module which is low in rejection rate.
It is still another objective of the present invention to provide a chip scale packaging method which is relatively more efficient than the prior art methods.
In keeping with the principle of the present invention, the foregoing objectives of the present invention are attained by the chip scale packaging method comprising a first step in which a substrate is provided on one side with a conductive layer, and on other side (nonconductive) with a chip adhering position. The chip adhering position is provided with one or more through holes, and a coating of a thermoplastic adhesive by stenciling. Thereafter, a semiconductor chip is disposed in the chip adhering position such that an active surface of the semiconductor chip is attached to the upper surface of the nonconductive side of the substrate, and that bond pads on the active surface are corresponding in location to the through holes. The substrate and the chip are subsequently heated under pressure for a predetermined period of time so that the chip is securely attached to the substrate. The bond pads of the active surface of the chip are connected by a plurality of bonding wires via the through holes with the bonding points of the substrate. The fringe of the chip and the areas of the through holes are provided with a passivation film of a nonconducting resin material. Finally, the substrate is transformed into a base by implanting the conductive layer of the substrate with a plurality of spherical bond points in a grid array fashion.
It is therefore readily apparent that the base of the semiconductor chip module formed by the method of the present invention is free from the drawbacks of the bases of the conventional semiconductor chip modules of the prior art. In light of the adhesive coating of the present invention being attained by stenciling, the coating process of the method of the present invention is done with efficiency and precision. In addition, the chip is directly implanted on the base, thereby minimizing the likelihood that the structural integrity of the base is undermined.
The foregoing objectives, features, and advantages of the present invention will be more readily understood upon a thoughtful deliberation of the following detailed description of two preferred embodiments of the present invention with reference to the accompanying drawings.
REFERENCES:
patent: 5731231 (1998-03-01), Miyasima
patent: 5811879 (1998-09-01), Akram
patent: 5953594 (1999-09-01), Bhatt et al.
patent: 6043109 (2000-03-01), Yang et al.
patent: 6060373 (2000-05-01), Saitoh
Biar Jin-Chyuan
Ho Kuo-Teh
Lee Cheng-Hui
Maa Chong-Ren
Browdy and Neimark
Picardat Kevin M.
United Test Center Inc.
LandOfFree
Chip scale packaging method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Chip scale packaging method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip scale packaging method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2604430