Chip scale package structure for an image sensor

Details Chip scale package structure for an image sensor Chip scale package structure for an image sensor

2007-02-06

2007-02-06

Epps, Georgia (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C250S208100, C257S433000

Reexamination Certificate

active

10662433

ABSTRACT:
A chip scale package (CSP) structure for an image sensor includes a semi-conductor image sense chip and multiple bonding pads formed on a top face of the semi-conductor image sense chip. A conducting wire extends from each of the multiple bonding pads by wire-bonding. Liquefied jelly-like material is covered with the top face of the semi-conductor image sense chip and forming a transparent layer on the top face of the semi-conductor image sense chip after drying up. The transparent layer has a thickness being equal to a height of each of the conduct wire relative to the top face of the semi-conductor image sense chip.

REFERENCES:
patent: 6211461 (2001-04-01), Park et al.
patent: 6342406 (2002-01-01), Glenn et al.
patent: 6476503 (2002-11-01), Imamura et al.
patent: 6580169 (2003-06-01), Sakuyama et al.
patent: 6731010 (2004-05-01), Horiuchi et al.

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