Chip scale package for power devices and method for making...

Details Chip scale package for power devices and method for making... Chip scale package for power devices and method for making...

2011-05-17

2011-05-17

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S750000, C257S698000, C257SE23069

Reexamination Certificate

active

07944048

ABSTRACT:
A chip scale package is disclosed that includes a semiconductor die further comprising an array of power buses electrically coupled to a high power integrated circuit, and a plurality of Under Bump Metallization (UBM) multi-layer power buses disposed parallel to one another and spanning substantially across the entire length of the semiconductor die. The plurality of multi-layer UBM power buses, electrically coupled to the array of power buses, further includes a thick metal layer configured in a geometric shape that have interconnection balls completely posited thereupon.

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patent: 6187615 (2001-02-01), Kim et al.
patent: 6900538 (2005-05-01), Alter et al.
patent: 6927471 (2005-08-01), Salmon
patent: 7768075 (2010-08-01), Yilmaz et al.
patent: 2003/0197278 (2003-10-01), Joshi et al.
patent: 2005/0062156 (2005-03-01), Alter et al.

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