Chip-scale package for integrated circuits

Details Chip-scale package for integrated circuits Chip-scale package for integrated circuits

2007-11-13

2007-11-13

Hollington, Jermele (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

11242296

ABSTRACT:
A chip-scale packaged IC is made by bonding one or more singulated die chips (from an IC wafer) to a common substrate, such as a single cap wafer (or a portion thereof) and cutting (singulating) the substrate to yield individual, chip-scale packaged ICs. Alternatively, each die chip is bonded to an individual, pre-cut cap. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid chip-scale packaged IC. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.

REFERENCES:
patent: 6291884 (2001-09-01), Glenn et al.
patent: 6656827 (2003-12-01), Tsao et al.
patent: 6882045 (2005-04-01), Massingill et al.
patent: 6900532 (2005-05-01), Kelkar et al.
patent: 7115997 (2006-10-01), Narayan et al.
Cluff et al., 10A.1 Electronic Packaging Technologies, CRC Press LLC (2001).

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