Chip scale package fabrication methods

Details Chip scale package fabrication methods Chip scale package fabrication methods

2008-04-25

2010-06-29

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S107000, C438S110000, C438S114000, C438S118000, C438S125000, C438S126000, C438S127000

Reexamination Certificate

active

07745261

ABSTRACT:
Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut.

REFERENCES:
patent: 5817541 (1998-10-01), Averkiou et al.
patent: 6420244 (2002-07-01), Lee
patent: 6732913 (2004-05-01), Alvarez
patent: 2003/0155641 (2003-08-01), Yeo et al.
patent: 2006/0046436 (2006-03-01), Ohuchi et al.
patent: 2006/0081966 (2006-04-01), Farnworth et al.
patent: 2008/0014677 (2008-01-01), Xiaochun et al.

Affiliated with

Also associated with

Rating

Chip scale package fabrication methods does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip scale package fabrication methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip scale package fabrication methods will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4247588