Chip scale package and method of fabricating the same

Details Chip scale package and method of fabricating the same Chip scale package and method of fabricating the same

2007-02-13

2007-02-13

Zarneke, David A. (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S113000, C438S107000, C257SE21506, C257SE21599

Reexamination Certificate

active

10988523

ABSTRACT:
Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises conductive layers with a designated depth formed on an upper and a lower surfaces of a chip, and electrode surfaces formed on the same side surfaces of the conductive layers, which are connected to corresponding connection pads of a printed circuit board. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.

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