Chip scale package and method of fabricating the same

Details Chip scale package and method of fabricating the same Chip scale package and method of fabricating the same

2005-01-11

2005-01-11

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S123000, C438S119000

Reexamination Certificate

active

06841416

ABSTRACT:
A method of fabricating a chip scale package includes: preparing a wafer including a plurality of chips; forming an insulating layer on the upper surface of the wafer except in areas of two upper terminals of each chip; forming an upper conductive layer on the insulating layer so as to be connected to the upper terminals of the chips; forming a lower conductive layer on the lower surface of the wafer so as to be connected to a lower terminals of each chip; first dicing the wafer so that one side of the chip scale package is formed; forming electrode surfaces on side surfaces of the upper and the lower conductive layers which are defined by the side of the chip scale package formed in the first dicing step; dividing the upper conductive layer of each chip into two areas each connected to one of the two upper terminals; and second dicing the wafer into package units.

REFERENCES:
patent: 5994167 (1999-11-01), Tai et al.
patent: 6074894 (2000-06-01), Suetsugu et al.
patent: 6177719 (2001-01-01), Huang et al.
patent: 6383838 (2002-05-01), Ryu

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