Chip scale package and method of fabricating the same

Details Chip scale package and method of fabricating the same Chip scale package and method of fabricating the same

2002-12-27

2004-11-09

Willie, Douglas (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S110000

Reexamination Certificate

active

06815257

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip scale package, and more particularly to a miniaturized chip scale package, which comprises a chip type device having a plurality of terminals on its one surface, and a method of fabricating the chip scale package.
2. Description of the Related Art
Generally, semiconductor devices such as transistors are packaged and these packaged devices are then mounted on a printed circuit board. Structurally, this package easily connects terminals of the semiconductor device to corresponding signal patterns of the printed circuit board and serves to protect the semiconductor device from external stresses, thereby improving reliability of the package.
In order to satisfy recent trends of miniaturization of semiconductor products, the semiconductor chip packages also have been miniaturized. Therefore, a chip scale package (also, referred to as a “Chip Size Package”) has been introduced.
FIG. 1
is a schematic cross-sectional view of a conventional chip scale package. The structure of the chip scale package
10
of
FIG. 1
employs a ceramic substrate
1
and is a diode package with two terminals.
With reference to
FIG. 1
, two via holes, i.e., a first via hole
2
a
and a second via hole
2
b
, are formed on the ceramic substrate
1
. The first and the second via holes
2
a
and
2
b
are filled with a conductive material so as to electrically connect the upper surface of the substrate
1
to the lower surface of the substrate
1
. Then, a first and a second upper conductive lands
3
a
and
3
b
are formed on the upper surfaces of the first and the second via holes
2
a
and
2
b
, respectively. A first and a second lower conductive lands
4
a
and
4
b
are formed on the lower surfaces of the first and the second via holes
2
a
and
2
b
, respectively. The second upper conductive land
3
b
is directly connected to a terminal formed on the lower surface of the diode
5
, i.e., a mounting surface of the diode
5
on a printed circuit board, and the first upper conductive land
3
a
is connected to the other terminal formed on the upper surface of the diode
5
by a wire
7
. A molding part
9
using a conventional resin is formed on the upper surface of the ceramic substrate
1
including the diode
5
in order to protect the diode
5
from the external stresses. Thereby, the manufacture of the package
10
is completed.
FIG. 2
is a cross-sectional view of a conventional chip scale package assembly, in which the chip scale package is mounted on the printed circuit board.
As shown in
FIG. 2
, the manufactured diode package
10
is mounted on the printed circuit board
20
by a reflow soldering. That is, the diode package
10
is mounted on the printed circuit board
20
by arranging the lower conductive lands
4
a
and
4
b
of the package
10
on the corresponding signal patterns of the printed circuit board
20
and by then connecting the lower conductive lands
4
a
and
4
b
to the signal patterns of the printed circuit board
20
with a solder
15
.
As shown in
FIGS. 1 and 2
, since the chip usually has a terminal on each of its two opposite surfaces, these terminals must be interconnected by wires. However, these wires require a large space on the upper surface of the chip, thereby increasing the overall height of the package. Further, since at least two via holes, corresponding to the number of terminals of the diode, must be formed on the ceramic substrate, an area as large as the total diameters of the via holes is further required. Moreover, in order not to connect the conductive lands formed on the upper and the lower surfaces of the via holes to each other, the conductive lands must be spaced from each other by a minimum interval. Therefore, the substrate has a large size so as to satisfy the aforementioned conditions, and the size of the substrate imposes a limit in miniaturizing the package.
The above-described diode has two terminals, each formed on the upper and the lower surfaces. However, an Integrated Circuit (IC) chip having a plurality of terminals on its one surface further requires a wire bonding step or employs a proper lead frame in order to interconnect the terminals to each other. That is, devices such as the IC chips have a plurality of terminals, thereby incurring a difficulty in miniaturizing the package including the device and complicating the fabrication process of the package.
Further, the substrate, which is employed by the above-described package, is a lead frame, a printed circuit board, or a ceramic substrate. These substrates are high-priced, thereby increasing the production cost of the package. Moreover, the conventional fabrication process of the package requires a wire-bonding step and a molding step as well as a die-bonding step, thereby being very complicated.
Accordingly, a packaging technique, which can minimize the size of the package and simplify its fabricating process, has been demanded.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a chip scale package, which is miniaturized and more simply fabricated, by forming an insulating layer on the upper surface of a chip except for terminal areas, by forming conductive layers on the insulating layer, and by forming electrode surfaces on the conductive layer so as to be connected to corresponding connection pads of a printed circuit board, thereby improving the reliability of the package.
It is another object of the present invention to provide a chip package assembly with an innovative mounting method according to the structure of the chip scale package.
It is a yet another object of the present invention to provide a method of fabricating the chip scale package.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a chip scale package comprising a chip having a plurality of terminals on its one surface, an insulating layer formed on the surface of the chip except for a plurality of terminal areas, a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance so as to be connected to each of a plurality of the terminals, and a plurality of electrode surfaces formed on each of the upper surfaces of a plurality of the conductive layers.
In accordance with another aspect of the present invention, there is provided a chip scale package assembly comprising a chip scale package and a printed circuit board. The chip scale package comprises a chip having a plurality of terminals on its one surface, an insulating layer formed on the surface of the chip except for a plurality of terminal areas, a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance so as to be connected to each of a plurality of the terminals, and a plurality of electrode surfaces formed on each of the upper surfaces of a plurality of the conductive layers. The printed circuit board comprises a plurality of connection pads for being connected to each of the electrode surfaces of the chip scale package, and circuit patterns connected to each of the connection pads.
In accordance with yet another aspect of the present invention, there is provided a method of fabricating a chip scale package, comprising the steps of preparing a wafer including a plurality of chips, each chip including a plurality of terminals on its one surface, forming an insulating layer on the upper surface of the wafer except for areas for forming the terminals, forming a conductive layer on the upper surface of the insulating layer so as to be connected to a plurality of the terminals, forming an electrode surface on the upper surface of the conductive layer, dividing the upper conductive layer formed on the insulating layer into two plural parts so as to connected to each of a plurality of the terminals, and dicing the wafer into a plurality of package units.


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