Chip scale package and method for manufacturing the same

Details Chip scale package and method for manufacturing the same Chip scale package and method for manufacturing the same

2007-06-04

2010-11-16

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S113000, C438S458000, C438S613000, C257SE23020, C257SE23021, C257SE23069

Reexamination Certificate

active

07833837

ABSTRACT:
A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.

REFERENCES:
patent: 5677576 (1997-10-01), Akagawa
patent: 6228687 (2001-05-01), Akram
patent: 7364983 (2008-04-01), Wang et al.
patent: 2002/0098620 (2002-07-01), Ding

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