Chip scale package and manufacturing method thereof

Details Chip scale package and manufacturing method thereof Chip scale package and manufacturing method thereof

1999-12-30

2001-04-24

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C438S108000, C257S698000, C257S778000, C257S787000

Reexamination Certificate

active

06221697

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, and more specifically to a chip scale package for use in packaging a central-pad die and a manufacturing method thereof.
2. Description of the Related Art
FIG. 1
depicts a conventional chip scale package
100
comprising an elastomer pad
110
with a slot
110
a
centrally defined therein interposed between a substrate
120
and a semiconductor chip
130
. One purpose of the elastomer pad
110
is to obtain suitable reliability by minimizing CTE mismatch stress between the substrate
120
and the semiconductor chip
130
.
The semiconductor chip
130
has a plurality of bonding pads
132
disposed centrally thereon. The substrate
120
includes a plurality of solder pads
122
and leads
124
provided on the upper surface thereof. The solder pads
122
are electrically connected to the corresponding leads
124
through conductive traces on the substrate
120
. The substrate
120
has a plurality of through-holes respectively corresponding to the solder pads
122
such that each of the solder pads
122
has at least a portion exposed from its corresponding through-hole for mounting a solder ball
126
. The substrate
120
has a slot
120
a
corresponding to the slot
110
a
of the elastomer pad
110
(see FIG.
2
). The leads
124
are bonded to their corresponding bonding pads
132
of the semiconductor chip
130
for electrically connecting the semiconductor chip
130
to the substrate
120
.
The encapsulation process of the chip scale package
100
typically comprises the steps of: (a) dispensing encapsulant into the slot
120
a
of the substrate
120
(see
FIG. 3
) to seal the leads
124
, and then curing the encapsulant by baking to form the package body
140
; and (b) flipping the product of step (a) over, then dispensing another encapsulant around the semiconductor chip
130
(see FIG.
4
), and curing the encapsulant by baking to form the package body
150
.
Since the encapsulation process of the chip scale package
100
must be carried out by repeating the steps of dispensing and curing twice, the encapsulation cycle time is prolonged. Therefore, the cost and cycle time for packaging a semiconductor chip is increased. Moreover, since the slot
120
a
of the substrate
120
is rather narrow, it is very difficult for dispensing the encapsulant into it. The encapsulant must be dispensed in precise amount and with proper flow, or it is easy to form flash on the substrate surface around the slot
120
a
, which in turn may contaminate the solder pads.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a chip scale package in which the encapsulation process thereof is carried out by a single step of dispensing and curing so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the package.
It is another object of the present invention to provide a chip scale package to reduce the occurrence of flash on the substrate surface around the slot during encapsulation, thereby assuring the solder joint reliability of the solder pads.
The chip scale package according to a preferred embodiment of the present invention mainly comprises two elastomer pads interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively disposed on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip has a plurality of bonding pads at its central area for electrically accessing the inner circuits thereof. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein the bonding pads of the semiconductor chip are corresponding to the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball. The chip scale package is electrically connected to outside circuits through the solder balls.
Since the two elastomer pads are respectively situated on both flanks of the slot of the substrate and keep a predetermined distance from the slot in such a manner that the space around the chip communicates with the slot of the substrate, the encapsulant dispensed around the semiconductor chip during encapsulation process of the package will automatically fill the slot of the substrate via capillary action.
Therefore, the encapsulation process of the package in accordance with the present invention can be carried out by a single step of dispensing and curing; hence, the encapsulation cycle time is shortened, which in turn increase UPH and reduces the cost for manufacturing the package. Moreover, since the encapsulant fills the slot of the substrate via capillary action, it is not easy for the encapsulant to overflow the slot and form flash on the substrate surface, thereby assuring the solder joint reliability of the solder pads.


REFERENCES:
patent: 5710071 (1998-01-01), Beddingfield et al.

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