Chip-scale package and carrier for use therewith

Details Chip-scale package and carrier for use therewith Chip-scale package and carrier for use therewith

2005-03-29

2005-03-29

Thai, Luan (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S668000, C257S738000, C257S774000, C257S778000

Reexamination Certificate

active

06873046

ABSTRACT:
A carrier for use in a chip-scale package includes a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device over which the carrier is to be positioned are at least partially filled with a quantity of conductive material. The carrier may also include laterally extending conductive traces that communicate electrically with the conductive material in the apertures. Contacts on a surface of the carrier may communicate with the conductive material within the apertures. A conductive bump may be disposed adjacent any of the contacts. The carrier may be positioned on a semiconductor device to form a chip-scale package. Such a chip-scale package may include a semiconductor device invertedly disposed over the carrier with bond pads of the semiconductor device being substantially aligned with apertures of the carrier.

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Jan Vardaman,What Does a CSP Cost ?, Advanced Packaging's Guide to Emerging Technologies, Jul./Aug. 1997.
U.S. Patent Application Publication 2003/0038378 A1 to Jacobs, dated Feb. 27, 2003.

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