Chip scale package

Details Chip scale package Chip scale package

2001-01-03

2002-09-24

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S781000, C257S780000, C257S779000, C257S772000, C257S737000, C257S738000, C257S795000, C257S668000

Reexamination Certificate

active

06455941

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a method for fabricating the same, and more particularly to a chip scale package (CSP).
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP) and flip chips. Both of them greatly reduce the amount of board real estate required when compared to the alternative ball grid array (BGA) and thin small outline package (TSOP). Typically, a CSP is 20 percent larger than the chip itself. The most obvious advantage of CSP is the size of the package; that is, the package is slightly larger than the chip. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die (KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and reworkability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path.
However, CSP has at least one disadvantage compared to conventional BGA and TSOP, namely, high cost per unit. However, this problem could be eliminated if chip-sized packages could be mass produced more easily.
Therefore, there is a need in the semiconductor packaging industry for CSP using mass production techniques at the wafer-level.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a chip scale package that can be mass produced at the wafer level.
To achieve above object, the present invention provides a chip scale package comprising a film substrate attached to the active surface of a semiconductor chip by an adhesive layer. The semiconductor chip has a plurality of bonding pads formed on the active surface thereof. The adhesive layer has a plurality of apertures formed corresponding to the bonding pads of the chip. The film substrate includes a film and a plurality of conductive leads formed thereon wherein the film has a plurality of first openings formed corresponding to the apertures of the adhesive layer and a plurality of second openings. Each lead on the film has a first end portion projecting into one of the first openings of the film and a second end portion exposed from one of the second openings of the film. Each aperture and corresponding first opening are filled with a conductive paste embedding the first end portion of one lead therein so as to electrically connect the bonding pads of the chip and the conductive leads of the film substrate. A plurality of solder bumps formed on the second end portions of leads through the second openings of the film.
The present invention further provides a method for making the chip scale package at the wafer level. The method comprises the following steps of: (a) providing a film with a glue formed thereon; (b) forming a plurality of first openings at predetermined positions of the film; (c) attaching a metal foil to the film through the glue thereon and the metal foil being patterned to form the desired circuitry including a plurality of conductive leads having a first end portions and a second end portions corresponding to the first openings of the film; (d) attaching the film substrate formed in step (e) to a wafer by an adhesive layer; (e) drilling through the film and the adhesive layer simultaneously at locations corresponding to the bonding pads on the wafer such that a plurality of apertures and second openings are formed in the adhesive layer and the film, respectively; (f) filling the apertures and the second openings with a conductive paste such that the first end portions of the leads are embedded therein so as to electrically connect the bonding pads to the conductive leads; (g) forming solder bumps on the second end portions of the leads; and (h) performing a dicing operation to obtain individual chip scale packages.


REFERENCES:
patent: 5905303 (1999-05-01), Kata et al.
patent: 5977624 (1999-11-01), Heo et al.

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