Chip-packaging with bonding options having a plurality of...

Details Chip-packaging with bonding options having a plurality of... Chip-packaging with bonding options having a plurality of...

2007-03-27

2007-03-27

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S786000

Reexamination Certificate

active

10709427

ABSTRACT:
Chip-packaging with bonding options having a plurality of package substrates. The chip-packaging includes first and second package substrates, a chip, and a lead. The chip having a plurality of bonding pads is mounted on the first package substrate. One of these bonding pads is connected to the first package substrate. Another bonding pad is connected to the second package substrate. The lead is connected to one bonding pad. The first and second package substrates have first and second voltages, respectfully. The first voltage and the second voltage are different, and each can be a GND voltage or a POWER voltage. With connection of these bonding pads with the lead or connection of these bonding pads with two package substrates, input ends or output ends in the chip could be connected to a GND voltage or a POWER voltage, or to one pin of the chip-packaging.

REFERENCES:
patent: 6339252 (2002-01-01), Niones et al.
patent: 6822319 (2004-11-01), Lau et al.
patent: 6995460 (2006-02-01), McLellan et al.

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