Chip packaging technique

Details Chip packaging technique Chip packaging technique

1994-09-27

2001-11-20

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S717000, C257S778000

Reexamination Certificate

active

06320257

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to chip packaging techniques and in particular to multichip modules (MCM) and to a new technique for the fabrication thereof. More particularly, the invention relates to packaging techniques for semiconductor chips, including microwave/RF chips and optical chips, and for the formation of 3D arrays.
BACKGROUND OF THE INVENTION
Multichip packaging approaches (MCP) or multichip modules (MCM) are known to provide significant performance enhancements over single chip packaging approaches. In MCP, several bare semiconductor chips (ICs) are mounted and interconnected on a common substrate through very high density interconnects. Advantages of this approach include a significant reduction in the overall size and weight of the package, which directly translates into reduced system size. Thus, first level advantages include:
1. Higher silicon packaging density—about a factor of
4
compared to surface mounted ICs on a printed wiring board (PWB).
2. Short chip-to-chip interconnections—at least a factor of two reduction in interconnect links.
3. Low dielectric constant materials—about three compared to nine for alumina and four to five for PWB materials.
4. Higher wiring density.
These benefits lead to the following secondary benefits:
1) increased system speed.
2) Increased reliability.
3) Reduced weight and volume.
4) Reduced power consumption (a factor of 4) for the same level of performance.
5) Reduced heat to be dissipated for the same level of performance.
While there are a number of currently utilized MCP approaches, existing MCP approaches suffer from at least one of the following two significant limitations. First, all such approaches require a hermetic package to protect the ICs. This is typically a metal or ceramic casing which encapsulates and seals the MCP/MCM to protect against both stray electrical fields and to protect it against environmental factors such as water vapor and gases.
The second limitation for most existing approaches is that the area beneath the ICs is shared both for electrical routing and heat removal. This results in some sharing of electrical and thermal paths, causing a thermal performance penalty. The thermal performance penalty results in the ICs operating at higher temperatures, thereby reducing the lifetime of the ICs. This reduces the reliability of systems in which the MCPs are utilized and increases the maintenance cost of such systems.
A need therefore exists for an improved MCP approach which achieves the electrical and environmental protection of the chips without the cost, size and weight disadvantages of an extra hermetic package and which eliminates the thermal performance penalty associated with the same area beneath the ICs being used for both electrical routing and heat removal.
Similar problems to those described above arise when packaging a single chip, when packaging microwave or RF components and when packaging optical components. A particular problem with the latter types of components is bringing output leads, for example transmission lines or optical fibers, through the side wall of the MCM package containing the optical and/or electrical devices. For example, with optical fibers, glass frits with ceramics and metal are utilized to seal around the fiber to retain the desired moisture and environmental protection. This is, however, an expensive process due to the cost of the materials as well as the labor involved. The heat involved in forming the glass seal also presents the risk of damaging electronic devices within the package during assembly. This sealing technique also has the disadvantage of making the part bulky and heavy, limiting its desirability for avionics and space applications. While attempts have been made to encapsulate fibers in ordinary polymers, such polymers do not provide a barrier to moisture, have limited structural integrity and coefficients of thermal expansion (CTE) which are high enough, and differ enough from that of the glass fibers as to create thermal cycling stresses. This reduces yields during assembly and adversely affects the long term reliability of the packages. The poor moisture barrier properties and poor mechanical properties also adversely affect the yield and reliability of the resulting packages. It is also important that the sealing technique utilized not cause mechanical stresses during packaging assembly since this can cause misalignment of fibers previously aligned, for example passively aligned, with corresponding devices. Such loss of alignment can adversely affect the performance and reliability of the device and can increase costs by adversely impacting the yield of usable devices. A need therefore exists for an improved technique for packaging devices having optical fibers or other information carrying leads exiting therefrom, which technique provides a good, thermally stable seal and moisture barrier.
SUMMARY OF THE INVENTION
In accordance with the above, this invention provides a package for at least one semiconductor chip and a method for the fabrication thereof which involves a substrate which includes at least a layer of a thermoplastic material having low moisture permeability, electrical interconnects formed on the substrate, at least one semiconductor chip bonded to selected ones of the electrical interconnects, a lid which preferably functions as a heat sink, and a hermetic seal formed around the chips between the substrate and the heat sink. Where the lid is a heat sink, it is preferably formed of a material having a high thermal conductivity and a coefficient of thermal expansion which substantially matches that of the chip and a thermal bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermoplastic material of the substrate is preferably a liquid crystal polymer (LCP) and the heat sink may also be formed at least in part of an LCP.
For some embodiments, the heat sink is a printed wiring board (PWB) which for at least one embodiment includes a cold-plate sandwiched between a pair of LCP layers, and thermal conduction pads extending from each thermal bond through an adjacent LCP layer to the cold-plate. The seal formed between the substrate and the heat sink may be a pinch seal. Where the heat sink is a PWB having electrical wiring thereon, electrical connections may be provided between the interconnects on the substrate and the electrical wiring on the PWB. For one embodiment, the substrate is of a material not having low moisture permeability, with a layer of LCP or other low moisture permeability thermoplastic coated or otherwise formed over the substrate and sealed to the lid.
Alternatively, the seal between the substrate and the heat sink may include at least one LCP interconnect element or frame between the substrate and the heat sink, with a seal being formed between the interconnect element or frame and the substrate and a seal being formed between the interconnect element and the heat sink. Where the chips have a signal conducting element such as a optical fiber array/bundle exiting therefrom, such signal conducting element may pass through and be sealed in the interconnect element. The heat sink is preferably formed of a material having a coefficient of thermal expansion (CTE) of two to ten ppm/C°, this material being for example a metal matrix composite or a polymer matrix composite. The heat sink may be formed of a machinable material which is bent to form a cavity in which the chips fit, with the edges of the heat sink being sealed to the substrate.
For preferred embodiments, the LCP is a multi-axially oriented material, for example Vectra™ or Xydar™. The chips may operate in the RF or microwave bands with the interconnects on the substrate being controlled impedance interconnects suitable for operation in the frequency band of the chips. The chips may also include optical components, either in addition to or instead of other components, with optical fibers being sealed into the substrate and aligned with corresponding optical component to transmit ligh

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