Chip packaging structure for improving reliability

Details Chip packaging structure for improving reliability Chip packaging structure for improving reliability

2008-04-22

2008-04-22

Clark, S. V. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Groove

C257S707000, C257S778000, C438S108000, C438S122000

Reexamination Certificate

active

11385920

ABSTRACT:
A novel chip packaging structure is disclosed. The chip packaging structure includes a flip chip having a chip backside, at least one concave stress-relieving structure provided in the chip backside, a carrier substrate bonded to the flip chip and an adhesive material interposed between the flip chip and the carrier substrate. During thermal testing and/or functioning of the flip chip, the stress-relieving structure reduces stresses between the flip chip and the carrier substrate and dissipates heat from the flip chip to reduce thermally-induced delamination stresses applied to the adhesive material and thereby enhances reliability of the flip chip.

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patent: 7022587 (2006-04-01), Konnemann
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patent: 2006/0209516 (2006-09-01), Chengalva et al.
patent: 2006/0278974 (2006-12-01), Hsiao et al.

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