Chip packaging structure and manufacturing process thereof

Details Chip packaging structure and manufacturing process thereof Chip packaging structure and manufacturing process thereof

2005-10-04

2005-10-04

Thai, Luan (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S125000, C438S122000, C438S108000

Reexamination Certificate

active

06951773

ABSTRACT:
A structure of a chip package and a process thereof are provided. The process of the chip package makes use of the TFT-LCD panel or IC process to increase the circuit layout density for high electrical performance. First, a multi-layer interconnection structure with pads of high layout density and thin fine circuits is formed on a base substrate with a large-area and high co-planarity surface, wherein the base substrate is made of quartz or glass or ceramics. Then, a chip is located on the top surface of the multi-layer interconnection structure by flip-chip or wire-bonding technology. Then, a substrate or a heat sink is attached on the top surface of the multi-layer interconnection structure for being a stiffener and providing mechanical support. Finally, the base substrate is removed and contacts are attached on the bottom surface of the multi-layer interconnection structure.

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patent: 6046077 (2000-04-01), Baba
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patent: 6472762 (2002-10-01), Kutlu
patent: 6501175 (2002-12-01), Yamashita

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