Chip packaging and connection for reduced EMI

Details Chip packaging and connection for reduced EMI Chip packaging and connection for reduced EMI

2005-03-22

2005-03-22

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S724000, C438S107000, C438S598000, C361S760000, C361S780000, C361S783000, C361S816000, C361S818000

Reexamination Certificate

active

06870252

ABSTRACT:
A chip package for reduced EMI. In one embodiment, a chip package includes a semiconductor chip mounted on a substrate. First and second horizontal conductors may be present within the substrate. The semiconductor chip is coupled to the first and second horizontal conductors by a first and second pluralities of vertical conductors, respectively. The silicon chip may receive power via the first horizontal conductor and the first plurality of vertical conductors. The first and second horizontal conductors are connected to external connectors by third and fourth pluralities of vertical conductors, respectively. One or more capacitors may be electrically coupled between the first and second horizontal conductors.

REFERENCES:
patent: 5294826 (1994-03-01), Marcantonio et al.
patent: 6219254 (2001-04-01), Akerling et al.
patent: 6294407 (2001-09-01), Jacobs
patent: 6297551 (2001-10-01), Dudderar et al.
patent: 6320257 (2001-11-01), Jayaraj et al.
patent: 6339253 (2002-01-01), Corisis
patent: 6525407 (2003-02-01), Drewery
patent: 6594153 (2003-07-01), Zu et al.
patent: 20010032738 (2001-10-01), Dibene et al.
patent: 03041466 (2003-05-01), None
Graf, “Modern Dictionary of Electronics,” p. 1112.

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