Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With means to prevent explosion of package
Reexamination Certificate
1999-09-02
2001-05-01
Graybill, David E. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With means to prevent explosion of package
Reexamination Certificate
active
06225687
ABSTRACT:
FIELD
The present invention relates generally to computer board and chip packaging, and more specifically to chip package design and manufacturing.
BACKGROUND
As input/output (I/O) speed and the total number of I/Os required for high performance semiconductor chips have increased dramatically, the need for increased numbers of interconnect lines with low line impedance variation in chip packages has increased as well. To address this need, manufacturers have used multi-layered packages where several layers of conductors are separated by layers of dielectric material.
In printed circuit board (PCB) and integrated circuit (IC) manufacture, often semiconductor dies are to be connected to a motherboard. Typically, a die is connected to a package, which is in turn connected to a motherboard. The motherboard typically receives multiple packages, thereby providing electrical connections between multiple semiconductor chips. One manner in which circuit dies can be mounted to a package is to “flip mount” the die to a small board designed to receive the die. When flip mounted, the die couples electrical signals to the package without the use of bond wires.
The package can have a core made of a common material such as glass epoxy, and can have additional layers laminated onto the core. These additional layers are also known as “built-up” layers. The built-up layers are typically formed from alternating layers of dielectric material and conductive material. Patterns may be built in the metal or conductive layer through various etching processes such as wet etching which are known in the art and will not be described further herein. Plated through holes called vias are used to make interconnects between various layers of metal. Using these layers and vias, several layers of interconnections may be built up.
Input/Output functions are typically accomplished using metal traces between the layers. Each trace has an impedance generated by its geometry and location on the package. Due to the manufacturing technology and material requirements, packages having built-up layers often include a number of degassing holes in the metal layers. Degassing holes allow gas to be evaporated during the manufacture of the package so that bubbles do not form in the package.
Traces may be routed over or under the degassing holes, or around the degassing holes, or a combination thereof. Since the traces are not in the same location on the package, and pass over varying amounts of non-metal areas caused by degassing holes in the metal layers, the traces have an impedance variation, or mismatch. A typical degassing hole pattern has a grid-like array of degassing holes aligned vertically between two layers, as is shown in FIG.
1
. In
FIG. 1
, the degassing holes
102
of the top and bottom layers are exactly aligned in the x and y directions. When traces such as trace
1
and trace
2
are used with a degassing hole alignment scheme as shown in
FIG. 1
, trace
1
has less metal from the conductive layers both above and below the trace than trace
2
, and an impedance variation between the traces results.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a semiconductor package having reduced trace impedance variation.
SUMMARY
In one embodiment, a device package includes a first conductive layer having a first grid of holes therethrough, where the first grid of holes is locatable relative to a first coordinate system. The device package also includes a second conductive layer also having a grid of holes therethrough. The second conductive layer is parallel to the first conductive layer, and the second grid of holes is also locatable relative to the first coordinate system. The device package also includes a plurality of signal traces disposed between the conductive layers, where the plurality of signal traces is locatable relative to a second coordinate system. A rotation axis is defined substantially perpendicular to the conductive layers, and the first coordinate system is rotated about the rotation axis between zero and 45 degrees relative to the second coordinate system.
REFERENCES:
patent: 6045927 (2000-04-01), Nakanishi et al.
Graybill David E.
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
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