Chip package structure and process for fabricating the same

Details Chip package structure and process for fabricating the same Chip package structure and process for fabricating the same

2007-04-03

2007-04-03

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

C257S778000, C257S737000, C257SE23136, C438S108000, C438S127000

Reexamination Certificate

active

10907400

ABSTRACT:
A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps are formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.

REFERENCES:
patent: 6335571 (2002-01-01), Capote et al.
patent: 2003/0170450 (2003-09-01), Stewart et al.
patent: 2004/0094842 (2004-05-01), Jimarez et al.

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