Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2008-06-27
2010-12-07
Tran, Minh-Loan T (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000, C257SE23123, C257SE23169, C257SE23175
Reexamination Certificate
active
07847414
ABSTRACT:
A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.
REFERENCES:
patent: 6022761 (2000-02-01), Grupen-Shemansky et al.
patent: 6168972 (2001-01-01), Wang et al.
patent: 6189208 (2001-02-01), Estes et al.
patent: 6252301 (2001-06-01), Gilleo et al.
patent: 6410415 (2002-06-01), Estes et al.
patent: 6555917 (2003-04-01), Heo
patent: 2001/0051392 (2001-12-01), Akram
patent: 2002/0028535 (2002-03-01), Brand
patent: 2002/0089067 (2002-07-01), Crane et al.
patent: 2003/0057552 (2003-03-01), Kainuma et al.
patent: 2006/0030071 (2006-02-01), Mizukoshi et al.
patent: 2007/0148817 (2007-06-01), Williams et al.
patent: 1956179 (2007-05-01), None
U.S. Office Action of U.S. Appl. No. 12/169,132, dated Jun. 24, 2009.
Chinese First Examination Report of China Application No. 2005101172129, dated Jan. 4, 2008.
Chinese First Examination Report of China Application No. 200810214686.9, dated Apr. 16, 2010.
Shen Geng-Shin
Wang David Wei
ChipMOS Technologies (Bermuda) Ltd.
ChipMOS Technologies Inc.
Cruz Leslie Pilar
J.C. Patents
Tran Minh-Loan T
LandOfFree
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