Chip package structure

Details Chip package structure Chip package structure

2007-05-31

2009-10-20

Smith, Zandra (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257SE23168, C257SE23169

Reexamination Certificate

active

07605461

ABSTRACT:
A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components.

REFERENCES:
patent: 5367196 (1994-11-01), Mahulikar et al.
patent: 5757070 (1998-05-01), Fritz
patent: 5793108 (1998-08-01), Nakanishi et al.
patent: 6900528 (2005-05-01), Mess et al.

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