Chip package structure

Details Chip package structure Chip package structure

2011-05-10

2011-05-10

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S686000, C257S723000, C257SE23169

Reexamination Certificate

active

07939950

ABSTRACT:
A chip package structure is provided. The chip package structure comprises a first substrate, a second substrate and a plurality of chips. Therein, one of the chips is connected to the first substrate and electrically connected to the first substrate through a via hole of the first substrate. Thereby, the second substrate does not need the via hole for electrical connection of chips and thus, the surface thereof is adapted to remain intact to allow for the disposition of conductive balls throughout the surface.

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patent: 2005/0167850 (2005-08-01), Moden
patent: 2005/0205979 (2005-09-01), Shin et al.
patent: 2006/0220209 (2006-10-01), Karnezos et al.
patent: 2007/0045803 (2007-03-01), Ye et al.

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