Chip package and manufacturing method thereof

Details Chip package and manufacturing method thereof Chip package and manufacturing method thereof

2009-01-21

2010-11-30

Ngo, Ngan (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Housing or package filled with solid or liquid electrically...

C257S690000, C257SE23011, C438S118000, C438S123000

Reexamination Certificate

active

07843054

ABSTRACT:
A chip package including a circuit substrate, a chip, a B-staged adhesive layer, a leadframe, a number of first bonding wires, a number of second bonding wires, and a number of third bonding wires. The chip is disposed on the circuit substrate. The B-staged adhesive layer is disposed on the circuit substrate. The leadframe is disposed on the circuit substrate and includes a number of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer. The first bonding wires are electrically connected between the chip and the circuit substrate. The second bonding wires are electrically connected between the chip and the leads. The third bonding wires are electrically connected between the leads and the circuit substrate. In addition, a manufacturing method of a chip package is also provided.

REFERENCES:
patent: 2006/0223207 (2006-10-01), Derderian et al.
patent: 2007/0080435 (2007-04-01), Lin
patent: 2009/0302485 (2009-12-01), Fan
patent: 2010/0019373 (2010-01-01), Fan
patent: 2010/0178501 (2010-07-01), Masuko et al.

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