Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Housing or package filled with solid or liquid electrically...
Reexamination Certificate
2008-04-08
2008-04-08
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Housing or package filled with solid or liquid electrically...
C257S701000, C438S122000
Reexamination Certificate
active
11230452
ABSTRACT:
A chip package and fabricating method thereof are provided to maintain the thermal dissipating efficiency and reduce the damage to the chip. The edge of the exposed portion would be cracked caused by external force because of the substrate of the chip is brittle. The crack in the edge of the chip will degrade the reliability and induce the malfunction of the chip. In this case, the chip is disposed at least one elastic element at the edges of the exposed side to reduce the risk of the crack in the chip.
REFERENCES:
patent: 6844622 (2005-01-01), Huang et al.
patent: 2003/0170450 (2003-09-01), Stewart et al.
patent: 2003/0178721 (2003-09-01), Lo et al.
patent: 574750 (2004-02-01), None
patent: 580742 (2004-03-01), None
IBM Technical Disclosure Bulletin “Multilevel Metallized Semiconductor chip Edge”, (Published Apr. 1988 vol. 30 issue 11 pp. 455-457).
Birch & Stewart Kolasch & Birch, LLP
Jackson Jerome
Valentine Jami M
VIA Technologies Inc.
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