Chip package

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step

Reexamination Certificate

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C257SE21503

Reexamination Certificate

active

07960214

ABSTRACT:
A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

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Chinese First Examination Report of China Application No. 2005101172129, dated on Jan. 4, 2008.
Chinese First Examination Report of China Patent Application No. 200810214686.9, dated Apr. 16, 2010.

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