Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2000-01-14
2002-10-08
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S618000, C257S619000
Reexamination Certificate
active
06462400
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits. More specifically, the invention concerns a Chip Outline Band (COB) structure for integrated circuits, particularly for integrated circuits subject to electromagnetic fields.
2. Discussion of the Related Art
Every integrated circuit device is provided with a perimeter edge structure suitable to prevent external agents, such as humidity and contaminants, from deteriorating the mechanical and/or electrical properties of the device, both during the manufacturing and in operation.
To this end, during the integrated circuit manufacturing, a so-called Chip Outline Band (COB) is formed along the external perimeter of the integrated circuit. The COB acts as a barrier against the leakage of humidity and/or contaminants not only during the integrated circuit manufacturing, but also after the operation of scribing or separation of the plurality of chips integrated in a same semiconductor wafer.
The COB is essentially a passive element that allows achievement of the desired effect of acting as a barrier against leaking of humidity and/or contaminants, and relaxing the mechanical stress at the edge of the integrated circuit. This effect is achieved thanks to the physical-topological structure of the COB. The presence of PN junctions further allows exploitation of the built-in potential of the PN junctions to create an electric field which acts against the diffusion of contaminant ions (e.g., sodium).
FIG. 1
shows in cross-section a conventional COB structure. At the periphery of a semiconductor substrate
1
of a chip, for example of the P type, where a field oxide region
2
terminates, an N type region
3
is formed. Region
3
forms substantially a ring running along the periphery of the chip. Region
3
is contacted by a first metal ring
4
, formed from a first metal layer, separated from the field oxide
2
by a dielectric layer
5
. Region
3
is also contacted by a second metal ring
6
, formed from a second metal layer, which over the field oxide
2
is separated from the first metal layer by an intermetal dielectric
7
. The whole chip is covered by a passivation layer
8
.
Several alternative embodiments for the COB structure shown in
FIG. 1
can be conceived, depending, for example, on the number of different metal layers and, more generally, depending on the specific manufacturing process.
For example, as shown in
FIG. 2
, a further N+ ring
9
, internal with respect to region
3
, can be provided, the N+ ring
9
being contacted by a respective metal ring
10
formed from the first metal layer.
The COB forms a sort of external frame of the integrated circuit chip. In this way, the COB protects the whole perimeter of the chip.
FIG. 3
is an electrical diagram of the COB. The COB itself is depicted as a ring, coupled through a reverse diode D
1
to the common ground GND of the integrated circuit, that is the substrate
1
. As shown, the COB is a structure substantially isolated from the remaining electronic circuit integrated in the chip, in that the COB is not connected to any active element of the integrated circuit. The isolation of the COB is guaranteed by the presence of diode D
1
(the PN junction diode formed by the N region
3
and the P substrate
1
).
There are an increasing number of applications wherein the integrated circuits operate immersed in not negligible electromagnetic fields. An example is given by contactless “Smart Cards”. Contactless Smart Cards work by taking the electric power supply from the surrounding electromagnetic field. The electromagnetic field is typically in the radio frequency range. The Smart Card is coupled to the electromagnetic field by means of a coil, conventionally external to the integrated circuit embedded in the card; however the coil could as well be integrated in the integrated circuit. The sinusoidal signal induced by the electromagnetic field in the coil is then rectified and used as a power supply. The exchange of information between the integrated circuit and the outside takes place through a coil, possibly by superimposing the information signal on a carrier wave.
In these devices, or more generally in devices which have to work immersed in an electromagnetic field, the COB can act as a disturbance element, since the COB's structure is essentially that of a coil, so the COB couples to the electromagnetic field. An induced sinusoidal signal can thus develop in the COB. The induced sinusoidal signal can forward bias the PN junction associated with the COB, so that carriers can be injected into the substrate. The disturbance depends on the frequency of the signal, and on the power of the electromagnetic radiation, as well as on the size of the integrated circuit chip, and on the particular COB structure. The disturbance can also vary with the baud rate of the contactless interface.
Thus, even if the provision of a COB is necessary in an integrated circuit chip, it can interfere with the correct operation of the integrated circuit.
In view of the state of the art described, it is an object of the present invention to provide a COB structure for an integrated circuit that is not affected by the aforementioned problems.
SUMMARY OF THE INVENTION
According to the present invention, this and other objects are achieved by a COB structure for an integrated circuit integrated in a semiconductor chip having a semiconductor substrate of a first conductivity type and biased at a common reference potential of the integrated circuit, the COB structure comprising a substantially annular region of a second conductivity type formed in the substrate along a periphery thereof, and at least one annular conductor region superimposed on and contacting the substantially annular region, wherein said substantially annular regions are electrically connected at said common reference potential.
REFERENCES:
patent: 4265685 (1981-05-01), Seki
patent: 5306945 (1994-04-01), Drummond
patent: 5559362 (1996-09-01), Narita
patent: 5814887 (1998-09-01), Tani
patent: 5969408 (1999-10-01), Perelli
patent: 63-128733 (1988-06-01), None
European Search Report from European Patent Application No. 99830007.3, filed Jan. 15, 1999.
Fratin Lorenzo
Pio Federico
Zuliani Paola
Kang Donghee
Loke Steven
Morris James H.
STMicroelectronics S.r.l.
Wolf Greenfield & Sacks P.C.
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