Chip-on-chip testing using BIST

Details Chip-on-chip testing using BIST Chip-on-chip testing using BIST

1999-04-07

2002-09-24

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C714S733000

Reexamination Certificate

active

06456101

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a novel and useful method for testing a chip-on-chip semiconductor device and a novel chip-on-chip device which implements this method.
BACKGROUND OF THE INVENTION
In the semi-conductor industry, designers are constantly designing integrated-circuit chips (IC chips) with the goal of decreasing their size and/or “footprint” so that the resulting IC chips can be utilized in smaller devices. Such efforts have resulted in, for example, cellular telephones which can fit in a shirt-pocket and calculators the size of credit cards.
It is customary to test IC chips before they are delivered to a purchaser to insure that the component is defect-free after being manufactured and/or that it remains in proper working condition during use. Such testing can be performed either before the IC chip is mounted into a device or after the chip has been mounted on a printed circuit board.
Testing of an entire IC chip prior to mounting is typically performed using an expensive VLSI test set (e.g., an Advantest Model T3341 VLSI tester) or other known dedicated testing device, using test vectors supplied by the system designer. This testing may be accomplished by applying the test vector to stimulate the inputs of the circuit and by monitoring the output response to detect the occurrence of faults.
Once a chip is mounted, IC chips are typically tested using well-known scan testing methods, although on-board testing using external test devices such as the VLSI test sets described above can also be performed.
Application specific integrated circuits (ASIC's) are IC chips that are designed and built for a specific application. Like most IC chips, ASIC's generally comprise a large number of individual circuit elements, for example, gates and flip-flops. It is common to include a built-in-self-test (BIST) circuit in ASIC's to enable testing of embedded portions of the ASIC (most often embedded memory) after the ASIC has been mounted into a device without requiring the use of external test equipment. Numerous examples of BIST circuits exist; see, for example, U.S. Pat. Nos. 5,872,793; 5,138,619; and 4,701,920; all of which are incorporated herein by reference.
FIG. 1
illustrates an IC having a BIST circuit built into the IC chip. As shown schematically in
FIG. 1
, a printed circuit board
12
has a plurality of solder pads
14
formed thereon. An IC chip
16
(e.g., an ASIC) is mounted via wire bond leads
14
and
18
. Typically, the leads
14
and
18
are connected via wire to form electrical connections there between. A BIST circuit
17
, formed as part of the IC chip
16
, provides for testing of portions of the IC chip
16
in a well known manner.
One development that has significantly reduced the size of devices containing IC chips is “chip-on-chip” technology (see, for example, U.S. Pat. No. 4,703,483, incorporated herein by reference). In the most general sense, chip-on-chip technology refers to the physical mounting of one chip atop another. Referring to
FIG. 2
, in a typical configuration, the IC chip
16
(referred to herein as the “primary chip”) of
FIG. 1
includes leads
20
formed thereon to provide points for connection to a second chip
22
(referred to herein as the “secondary chip”) having leads
24
formed on its underside. The configuration illustrated in
FIG. 2
results in a reduction of the footprint of the combined chips (i.e., secondary chip
22
does not take up any space on the printed circuit board
12
). For the purpose of simplicity the physical connection of the chips to each other and to the printed circuit board are illustrated as solder pad/solder joint connections. In practice, these connections could be made using any known method for attaching chips to each other or to a printed circuit board.
Certain problems exist when it comes to testing a chip-on-chip device. When two chips are stacked as shown in
FIG. 2
, a standard testing device or testing system can only be used with great difficulty. For example, to test secondary chip
22
using an external testing device, it must be accessed via the electrical connections of primary chip
16
. The test equipment must “navigate” through the logic of the primary chip
16
to get to the secondary chip
22
. Thus, test vectors need to be written which will function on secondary chip
22
taking into account the circuitry of primary chip
16
. Likewise, if the primary IC chip
16
is equipped with BIST as shown in
FIG. 2
, the BIST circuit must be able to perform the testing of the secondary IC chip
22
in addition to the testing of the portions of primary IC chip
16
that require BIST testing. These requirements are quite complicated and time-consuming to achieve, and require a great deal of effort on the part of the IC chip designer.
SUMMARY OF THE INVENTION
The present invention provides an improved method and apparatus for testing chip-on-chip semi-conductor devices. The invention accomplishes this objective by the inclusion of an auxiliary BIST circuit in the primary chip to which the secondary chip is attached, thereby allowing testing of the secondary chip using the auxiliary BIST circuit.
In a preferred embodiment the present invention comprises an integrated circuit having a primary IC chip and a secondary IC chip electrically connected to each other, the primary IC including an auxiliary BIST circuit for testing the secondary IC. The primary IC chip may further include a primary BIST circuit for testing of portions of the primary IC chip.


REFERENCES:
patent: 4697095 (1987-09-01), Fujii
patent: 4701920 (1987-10-01), Resnick et al.
patent: 4703483 (1987-10-01), Enomoto et al.
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5872793 (1999-02-01), Attaway et al.
patent: 5987632 (1999-11-01), Irrinki et al.
patent: 6065134 (2000-05-01), Bair et al.

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