Chip-on-chip semiconductor device having selectable terminal con

Details Chip-on-chip semiconductor device having selectable terminal con Chip-on-chip semiconductor device having selectable terminal con

1985-10-02

1987-09-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307465, 307475, 307585, 307303, 324 73R, 34082583, 357 75, 371 15, H03K 17693

Patent

active

046970959

ABSTRACT:
A circuit configuration in a chip for a semiconductor device based on so-called chip-on-chip technology. The chip has a selecting circuit which switches, according to the control signals supplied thereto, an input of an internal circuit formed on the chip to connect to an output of the internal circuit or to an input terminal for receiving signals from another chip with which the chip is to be interconnected in a completed chip-on-chip structure. The control signals to operate the selecting circuit can be supplied without using large terminals to be connected to an external circuit, by simple impedance means and biasing means respectively provided for the chip and the other chip.

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Kraynak et al., "Wafer-Chip Assembly for Large-Scale Integration", IEEE Trans. Elect. Devices, vol. ED-15, No. 9, 9-1968, pp. 660-663.
"Bipolar-FET Package Design", IBM T.D.B., vol. 28, No. 2 L, Jul. 1985, p. 523.

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