Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2002-07-30
2004-02-03
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S462000
Reexamination Certificate
active
06686224
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip manufacturing method for manufacturing circuit chips from a circuit substrate, and more particularly, to a chip manufacturing method for manufacturing circuit chips with which a circuit test through test pads is performed.
2. Description of the Related Art
At present, circuit chips comprising integrated circuits are used in a variety of electronic apparatus, and a variety of methods also exist for manufacturing and testing such circuit chips. A typical chip manufacturing method involves forming a large number of rectangular integrated circuits in an array on the surface of a silicon wafer, which serves as circuit substrates of resulting integrated circuits, through scribing lines, and sectioning the silicon wafer along the scribing lines by scribing or dicing to form a large number of circuit chips, each of which comprises the integrated circuit.
When circuit chips are manufactured in the foregoing manner, integrated circuits may be additionally formed with test wirings and test pads for testing the integrated circuits. In this event, the test pads have been connected to associated parts through the test wirings when the integrated circuits are formed, and, for example, the silicon wafer is sectioned to form circuit chips before a tester is connected to the test pads for testing the integrated circuit in each circuit chip.
In another technique, a tester is connected to test pads of integrated circuits formed on a silicon wafer for testing the integrated circuits, and the silicon wafer is sectioned to form circuit chips after the circuit test is completed. In such a technique which tests the integrated circuits before the silicon wafer is sectioned, test pads are not required for the circuit chips sectioned from the silicon wafer.
On the other hand, when a silicon wafer is sectioned along scribe lines by dicing or the like, the scribe lines must have a predetermined width. Japanese Patent examined Publications Nos. 07-120696B(62199026A), 08-030820B(62207970A) and 08-008288B(06244252A), Japanese examined Patent No. 03093216B(03022456A), and the like disclose techniques which eliminate test pads that would otherwise remain on circuit chips by forming the test pads on scribe lines which are defined as scribe regions.
In such a circuit chip, since test pads are formed in the scribe region used for sectioning a silicon wafer, no test pads exist on a sectioned circuit chip. It is therefore possible to reduce the size of the circuit chip, and prevent a malicious user from fraudulently accessing an integrated circuit in the circuit chip through test pads.
In recent years, however, due to an improved accuracy of scribing and dicing, and increasingly narrower scribe lines, it becomes increasingly difficult to form test pads on the scribe lines used as a scribe region.
While test pads can be formed in scribe regions in the aforementioned technique of sectioning a silicon wafer after integrated circuits are tested, test pads cannot be formed in scribe regions in a technique which sections a silicon wafer before integrated circuits are tested.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a chip manufacturing method which is capable of preventing fraudulent accesses to circuit chips even with a technique which sections a silicon wafer along highly accurate and narrow scribe lines before integrated circuits are tested.
A first chip manufacturing method according to the present invention, similar to the prior art, forms a number of substantially rectangular integrated circuits, each connected to at least one test pad through a test wiring, arranged through section lines on the surface of a circuit substrate, sections the circuit substrate along the section lines into the individual integrated circuits to form a number of circuit chips, and conducts a circuit test through the test pads associated with the circuit chips.
Specifically, a first and a second section lines are set in parallel to each other along at least one of four sides of each of the substantially rectangular integrated circuit arranged and formed on the surface of the circuit substrate, and the test pads and/or at least part of each of the test wirings are formed in gaps between the first and second section lines.
The circuit test is conducted after sectioning the circuit substrate along the first section line positioned outside, and each circuit chip is cut along the second section line after conducting the circuit test to remove from the circuit chip a portion thereof in which the test pad and/or at least the part of the test wiring are formed.
Since the test pads connected to integrated circuits through the test wirings remain on the circuit chips when they are sectioned individually from the circuit substrate, the circuit test can be simply and satisfactorily conducted on the integrated circuits through the test pads.
On the other hand, since the test pads connected to the integrated circuits through the test wirings do not remain when the circuit chips are shipped after the circuit test is completed, it is possible to securely prevent fraudulent accesses to the integrated circuits through the test pads.
In a second chip manufacturing method according to the present invention, integrated circuits of circuit chips which undergo a circuit test are cut from a circuit substrate along first section lines positioned outside, while integrated circuits of circuit chips which do not undergo a circuit test are cut from the circuit substrate along second section lines positioned inside.
Thus, the test pads remain on circuit chips which undergo the circuit test before shipment, so that the integrated circuits can be simply and satisfactorily tested through the test pads. On the other hand, there is no test pad which would be connected to the integrated circuits through the test wirings on circuit chips, which are shipped without the circuit test conducted thereon, so that it is possible to securely prevent fraudulent accesses to the integrated circuits through the test pads.
In a third chip manufacturing method according to the present invention, similar to the prior art, a circuit test is conducted on at least some of integrated circuits formed on a circuit substrate through test pads, and the circuit substrate is sectioned along section lines into individual integrated circuits, after the circuit test is completed, to form a number of circuit chips. After the circuit test is completed, the circuit substrate is sectioned along at least second section lines positioned inside.
Thus, since the test pads connected to the integrated circuits through the test wirings remain on the circuit chips at the time the circuit test is conducted thereon, the integrated circuits can be simply and satisfactorily tested through the test pads. On the other hand, the test pads connected to the integrated circuits through the test wirings do not remain on the circuit chips when they are shipped after the circuit test is completed, so that it is possible to securely prevent fraudulent accesses to the integrated circuits through the test pads.
As another aspect of the present invention, the test pad is formed in a gap between the first and second section lines, and the test wiring connects the integrated circuit positioned inside the second section line to the test pads positioned outside the second section line.
Therefore, as a portion outside the second section line is cut away from the circuit chip, no test pad remains on the circuit chip, so that fraudulent accesses can be prevented without fail.
Alternatively, the test pad is formed within the integrated circuit which is positioned inside the second section line, and a portion of the test wiring connecting the integrated circuit to the test pad, both positioned inside the second section line, is routed in a gap between the first and second section lines.
Therefore, as a portion outside the second section line is cut away from the circuit chip, the test wiring connecting the integ
Blum David S
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
Thompson Craig A.
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