Chip-level underfill method of manufacture

Details Chip-level underfill method of manufacture Chip-level underfill method of manufacture

2011-05-31

2011-05-31

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S026000, C438S068000, C438S464000, C438S458000

Reexamination Certificate

active

07951648

ABSTRACT:
A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern, which is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. A curable underfill coating is applied to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The scanned and stored alignment pattern is delivered to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure. The coated semiconductor chip is placed in the alignment and joining device so that when the scanned and stored alignment pattern is activated the alignment and joining device positions the coated semiconductor chip so that the first electrical interconnect structure is aligned to make electrical contact with the second electrical interconnect structure. The alignment and joining device is activated to join the coated semiconductor chip to the substrate.

REFERENCES:
patent: 6919420 (2005-07-01), Buchwalter et al.
patent: 6924171 (2005-08-01), Buchwalter et al.
patent: 7391119 (2008-06-01), Shi
patent: 2005/0218517 (2005-10-01), Capote et al.
patent: 2006/0043608 (2006-03-01), Bernier et al.
patent: 2008/0265445 (2008-10-01), Feger et al.

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