Chip-level or symbol-level equalizer structure for multiple...

Pulse or digital communications – Spread spectrum – Direct sequence

Reexamination Certificate

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C375S150000, C375S267000

Reexamination Certificate

active

10783049

ABSTRACT:
Disclosed is a chip-level or a symbol-level equalizer structure for a multiple transmit and receiver antenna architecture system that is suitable for use on the WCDMA downlink. The equalizer structure takes into account the difference in the natures of inter-antenna interference and multiple access interference and suppresses both inter-antenna interference and multiple access interference (MAI). Enhanced receiver performance is achieved with a reasonable implementation complexity. The use of the CDMA receiver architecture, in accordance with this invention, enables the realization of increased data rates for the end user. The CDMA receiver architecture can also be applied in conjunction with space-time transmit diversity (STTD) system architectures.

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patent: 1289182 (2003-03-01), None
patent: 1357693 (2003-10-01), None
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“Multi-antenna Transceiver Techniques for 3G and Beyond”, Ari Hottinen et al., John Wiley & Sons, Chichester, UK, 2003, pp. 123-131.

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