Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
1999-05-18
2001-10-09
Abraham, Fetsum (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S210000, C257S211000
Reexamination Certificate
active
06300651
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device.
BACKGROUND OF THE INVENTION
In recent semiconductor memory devices, integration of memories becomes higher, and the area of pads occupied in a chip becomes increased. As to the arrangement of bonding pads, they are arranged on the periphery or in the center of a chip. Especially, in the latter case of a center bonding structure, longitudinal side length of the chip must be prolonged in order to arrange the pads due to the largeness of their number. On this account, it is necessary to reduce the number of wires each passing through an interstitial space between opposing pads and to shorten an interstitial distance between the pads.
A layout of a conventional semiconductor device will be explained below in reference to the accompanying drawings. FIGS.
3
(
a
) through
3
(
c
) are explanatory views showing a schematic layout of a conventional semiconductor device. FIG.
3
(
a
) is a layout view showing the peripheral part of bonding pads of a center bonding structure; FIG.
3
(
b
), a layout view showing a wire connection part of FIG.
3
(
a
); and FIG.
3
(
c
), an explanatory view showing a layout of another center bonding structure.
As shown in FIGS.
3
(
c
) through
3
(
c
) shelves
103
for arranging second peripheral circuit elements including input/output circuit element, internal voltage-dropping circuit element, logic circuit element and the like are positioned on a chip of a center bonding structure so as to sandwich bonding pads
104
. A self
102
for arranging first peripheral circuit elements such as data-amplifying circuit element, word line driving circuit element and the like is positioned outside each of the shelves
103
. Further, memory arrays
101
are positioned outside the shelves
102
, respectively. Wires for transmitting electric signals are formed between the shelves
102
for arranging first peripheral circuit elements or between the shelves
103
for arranging second peripheral circuit elements. The shelves
102
are positioned along both sides of the pads.
SUMMARY OF THE DISCLOSURE
However, in the course of the investigations toward the present invention the following problems have been encountered. Namely, in such a structure as disclosed above wherein the bonding pads are centered and the shelves
102
and
103
are positioned on both sides thereof, it may be possible to reduce the difference in data-accessing speeds between banks. However, this layout causes a problem that an increase cannot be avoided in the number of wires each passing through an interstitial space between two of the pads
104
correspondingly to the number of connection wires
108
each of which connects two shelves
103
which are disposed opposing each other through the intermediary of the pads.
In order to decrease the number of the wires each passing through the interstitial space, it is necessary to position longitudinal wires
106
at both sides of the pads
104
as shown in FIG.
3
(
c
). This structure causes a problem that the width or distance along the transverse direction (up and down direction in the figure) of a chip should be increased, which results in increasing the chip size.
The present invention has been made in consideration of the above problems. An essential object of the present invention is to provide a semiconductor device capable of making the interstitial space between two of the pads
104
narrow and thereby decreasing the chip size without increasing the difference in accessing speeds between banks.
A semiconductor device of the present invention comprises a sequence of pads, memory arrays positioned along both sides thereof and peripheral circuit element groups positioned between the memory arrays. The semiconductor device is improved in that the peripheral circuit element groups which do not affect circuit operation are positioned on one side of the sequence of pads so as to reduce the number of wires connected to the peripheral circuit element groups passing through an interstitial area between adjacent two of the pads.
The present invention also provides a semiconductor device comprising a sequence of pads, memory arrays positioned along both sides thereof, and first and second peripheral circuit element groups each positioned between the memory arrays. The first peripheral circuit element groups include circuit elements which require to be positioned in symmetry relative to the sequence of the pads from the view of circuit properties. In contrast to this, each of the second peripheral circuit element groups includes circuit elements which do not require to be positioned in symmetry relative to the sequence of the pad from the view of circuit properties. The semiconductor device of the present invention is improved in that the second peripheral circuit element groups are positioned so that wires each connected to two of the second peripheral circuit element groups do not pass through an interstitial area between neighboring two of the pads. The second peripheral circuit element groups may be positioned on one side of the sequence of the pads.
The first peripheral circuit element groups preferably include amplifying circuit element and driving circuit element or other circuits having the equivalent function of these circuit elements, and the second peripheral circuit element groups preferably include input/output circuit element and logic circuit, or other circuits having the equivalent function of these circuit elements.
REFERENCES:
patent: 4499484 (1985-02-01), Tanizawa et al.
patent: 5109265 (1992-04-01), Utesch et al.
patent: 5361223 (1994-11-01), Inoue et al.
patent: 5619472 (1997-04-01), Okamura
patent: 5898636 (1999-04-01), Isomura et al.
patent: 5907166 (1999-05-01), Casper et al.
patent: 6069812 (2000-05-01), Lee et al.
patent: 6-85185 (1994-03-01), None
patent: 9-69294 (1997-03-01), None
patent: 9-91978 (1997-04-01), None
patent: 9-198882 (1997-07-01), None
patent: 9-251785 (1997-09-01), None
patent: 98-6287 (1998-03-01), None
patent: WO96/24138 (1996-08-01), None
Japanese Office Action dated Apr. 6, 1999, with partial translation.
Abraham Fetsum
McGinn & Gibb PLLC
NEC Corporation
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