Chip interconnection structure using stub terminals

Details Chip interconnection structure using stub terminals Chip interconnection structure using stub terminals

1999-01-04

2001-08-07

Graybill, David E. (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S613000

Reexamination Certificate

active

06271059

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to fabricating integrated circuit structures, and more particularly to a structure and method for electrically interconnecting prefabricated circuit chips.
2. Background Art
An example of a technique for fabricating an integrated circuit structure having a stepped interposer is described in U.S. Pat. No. 5,714,800 issued Feb. 3, 1998 to Thompson entitled INTEGRATED CIRCUIT ASSEMBLY HAVING A STEPPED INTERPOSER AND METHOD. This reference discloses a method of forming an integrated circuit assembly having a stepped interposer, an integrated circuit die, and an encapsulant. The stepped interposer is coupled to the die and provides contact regions free from encapsulant.
U.S. Pat. No. 5,598,033 issued Jan. 28, 1997 to Behien et al. entitled MICRO BGA STACKING SCHEME describes a stacking method for micro-BGA circuits.
U.S. Pat. No. 5,109,320 issued Apr. 28, 1992 to Bourdelaise et al. entitled SYSTEM FOR INTERCONNECTING INTEGRATED CIRCUIT DIES TO A PRINTED WIRING BOARD discloses a system for electrically and mechanically connecting an integrated circuit board to a solderless printed circuit board.
The publication WAFER INTERCONNECTIONS by Blum et al. in the IBM Technical Disclosure Bulletin, Vol. 32 No. 108, Mar. 1990 at page 276 discloses a silicon wafer interconnector based on liquid contacting.
The publication HIGH-PERFORMANCE TEST SYSTEM by Klink et al. In the IBM Technical Disclosure Bulletin, Vol. 33 No. 14, Jun. 1990 at page 124 discloses a silicon carrier that is metallized and brought into contact with a wafer.
Co-pending U.S. patent application Ser. No. 09/039962, filed Mar. 16, 1998 and entitled METHOD AND APPARATUS FOR INTERCONNECTING MULTIPLE CIRCUIT CHIPS discloses a method for forming tetragonal contacts for mechanically and electrically interconnecting integrated circuit chips.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a structure and fabrication method for mechanically and electrically interconnecting a plurality of circuit chips.
A further object of the present invention is to provide a selective etching method for forming protrusion terminals on the front and/or back surfaces of a connector or interposer for making mechanical and electrical contact between two circuit chips.
Another object of the present invention is to provide a circuit chip connector or interposer having one or more protrusion terminals on the top and/or bottom surfaces to align with recesses in circuit chips to be mechanically and electrically connected.
Still another object of the present invention is to provide a connector using protrusion terminals for electrically and mechanically interconnecting a plurality of standard circuit chips without modification to the original dies.
A still further object of the present invention is to provide a selective etching method for forming a chip connector having truncated pyramidal protrusions.
Other features, advantages and benefits of the present invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings which are incorporated in and constitute a part of this invention and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure.


REFERENCES:
patent: 5109320 (1992-04-01), Bourdelaise et al.
patent: 5592736 (1997-01-01), Akram et al.
patent: 5598033 (1997-01-01), Behlen et al.
patent: 5714800 (1998-02-01), Thompson
patent: 6020624 (2000-02-01), Wood et al.
patent: 6069025 (2000-05-01), Kim
IBM Technical Disclosure Bulletin, High Performance Test System, E. Klink et al., vol. 33, No. 1A Jun. 1990, p. 124.
IBM Technical Disclosure Bulletin, Wafer Interconnectors, A. Blum et al., vol. 32, No. 10B, Mar. 1990, p. 276.

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