Chip interconnect bus

Details Chip interconnect bus Chip interconnect bus

2002-03-16

2004-03-16

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular chip input/output means

C257S207000, C257S211000, C257S210000, C257S620000, C385S017000, C385S018000, C385S016000, C359S223100, C359S872000, C359S871000, C359S877000, C438S692000, C361S222000, C361S220000, C361S233000, C361S234000

Reexamination Certificate

active

06707077

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a microelectromechanical system, and more particularly to various attributes of an electrical trace bus that routes electrical signals throughout at least a portion of the system.
BACKGROUND OF THE INVENTION
There are a number of microfabrication technologies that have been utilized for making microstructures (e.g., micromechanical devices, microelectromechanical devices) by what may be characterized as micromachining, including LIGA (Lithography, Galvonoforming, Abforming), SLIGA (sacrificial LIGA), bulk micromachining, surface micromachining, micro electrodischarge machining (EDM), laser micromachining, 3-D stereolithography, and other techniques. Bulk micromachining has been utilized for making relatively simple it micromechanical structures. Bulk micromachining generally entails cutting or machining a bulk substrate using an appropriate etchant (e.g., using liquid crystal-plane selective etchants; using deep reactive ion etching techniques). Another micromachining technique that allows for the formation of significantly more complex microstructures is surface micromachining. Surface (micromachining generally entails depositing alternate layers of structural material and sacrificial material using an appropriate substrate (e.g., a silicon wafer) which functions as the foundation for the resulting microstructure. Various patterning operations (collectively including masking, etching, and mask removal operations) may be executed on one or more of these layers before the next layer is deposited so as to define the desired microstructure. After the microstructure has been defined in this general manner, the various sacrificial layers are removed by exposing the microstructure and the various sacrificial layers to one or more etchants. This is commonly called “releasing” the microstructure from the substrate, typically to allow at least some degree of relative movement between the microstructure and the substrate.
It has been proposed to fabricate various types of optical switch configurations using various micromachining fabrication techniques. One of the issues regarding these types of optical switches is the number of mirrors that may be placed on a die. A die is commonly referred to as that area defined by one field of a stepper that is utilized to lay out the die. Reducing the size of the mirrors in order to realize the desired number of mirrors on a die may present various types of issues. For instance, there are of course practical limits as to how small the mirrors can be fabricated, which thereby limits the number of ports for the optical switch. Also, the optical requirements of the system using the mirrors may require mirrors larger than some minimum size. Therefore, it may not be possible to fabricate the optical switch with a certain number of ports using a single die. This presents a challenge regarding how to route electrical signals.
BRIEF SUMMARY OF THE INVENTION
A first aspect of the present invention is embodied by a chip that includes a first row of a plurality of chip sections. Each chip section is of one die width. The chip further includes a second and third rows of a plurality of microstructure assemblies on each chip section. Each microstructure assembly may include at least one electrical load-based microstructure. In any case, a first electrical trace bus is located between the second and third rows on each chip section. This electrical trace bus is collectively defined by a plurality of electrical traces. A plurality of first and second off-chip electrical contacts are disposed on a pair of different chip sections, and both are disposed at least generally beyond an end of at least one of the second and third rows. Each of the first and second off-chip electrical contacts are electrically interconnected with a single electrical path that leads to one electrical load-based microstructure in one of the second and third rows on one of the chip sections. Moreover, the electrical trace bus on each chip section is electrically interconnected with at least some of the electrical load-based microstructures in at least one of the second and third rows that are on the same chip section.
Various refinements exist of the features noted in relation to the first aspect of the present invention. Further features may also be incorporated in the first aspect of the present invention as well. These refinements and additional features may exist individually or in any combination. A “chip” as used herein means a continuous section that may be sawed, diced, or otherwise separated from a wafer. A dimension of each chip section that corresponds with a direction in which the associated first row at least generally extends may correspond with a single exposure field of a photolithographic stepper, or stated another way each chip section may be of one die width. As used herein, a “die” means an area encompassed by a single exposure field of a photolithographic stepper. Each chip section may define at least a portion of a die. Another option is for each chip section to encompass at least one entire die.
Each chip section may include a plurality of the second and third rows in the case of the first aspect, with each pair of second and third rows having a first electrical trace bus located therebetween. A plurality of the noted first rows also may be utilized by the chip of the first aspect. Consider that each first row extends in at least generally a first direction, such that the plurality of first rows would be disposed in at least generally parallel relation. The plurality of first rows may collectively span at least one die in a second direction that is perpendicular to the noted first direction. Stated another way and where each first row extends in a direction corresponding with a die width, the chip of the first aspect may include at least one die height. Another embodiment has the plurality of first rows collectively span a non-integer number of die in a second direction that is perpendicular to the noted first direction. Stated another way and where each first row extends in a direction corresponding with a die width, the chip may include at least one partial die height.
Various arrangements of the first electrical trace bus associated with the first aspect may be utilized. For instance, the first electrical trace bus on each chip section may be limited to the space between the second row and third rows of microstructure assemblies on the same chip section, except for those individual electrical traces that extend away from the first electrical trace bus for interconnection with the relevant electrical load-based microstructure and where the bus progresses between adjacent chip sections. In one embodiment, the first electrical trace bus in each chip section is interconnected with at least some of the electrical load-based microstructures in one of the second and third rows on the same chip section, and none of the electrical load-based microstructures in the other of the second and third rows on the same chip section. In another embodiment, the first electrical trace bus on each chip section is interconnected with at least some of the electrical load-based microstructures in both of the second and third rows on the same chip section.
Each microstructure assembly of the first aspect may be a mirror assembly that includes a mirror, an elevation structure interconnected with the mirror, and at least one actuator interconnected with the elevation structure. Each actuator of each mirror assembly may be electrically interconnected with a single first or second off-chip electrical contact and accessed by the first electrical trace bus on at least one of the chip sections. In any case, the chip may collectively define a mirror array. These mirror assemblies may be disposed on each of the chip sections such that a center of each mirror in the second row is disposed along a common reference line, and such that that a center of each mirror in the third row is disposed along a common reference line. In one embodiment

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