Chip interconnect and packaging deposition methods and...

Details Chip interconnect and packaging deposition methods and... Chip interconnect and packaging deposition methods and...

2006-12-12

2006-12-12

Wong, Edna (Department: 1753)

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

C205S123000, C205S221000, C205S222000

Reexamination Certificate

active

07147766

ABSTRACT:
The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

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