Chip interconnect and packaging deposition methods and...

Details Chip interconnect and packaging deposition methods and... Chip interconnect and packaging deposition methods and...

1999-09-17

2002-03-12

Valentine, Donald R. (Department: 1741)

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Simultaneous deplating and plating

C205S640000

Reexamination Certificate

active

06355153

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating high performance chip interconnects and packages. More particularly, the present invention is directed to a method for insitu-selectively removing portions of a seed layer from a top surface of a substrate while preventing removal of the seed layer from the cavities formed therein. Moreover, the present invention discloses methods for depositing a conductive material in cavities of a substrate.
BACKGROUND OF THE INVENTION
Depositing a metal/conductive material in cavities (trenches, holes, and vias) of a substrate or workpiece has important and broad application in the semiconductor and non-semiconductor industries. Conductive materials are deposited in cavities of the substrate to interconnect layers and components contained therein. In recent times, there is great interest in fabricating chips and devices with very high aspect ratio and sub micron level features (e.g., below 0.25 um). As a result, copper is the preferred conductive material of choice as it provides better conductivity and reliability than, for example, aluminum or aluminum alloys.
FIGS. 1A-1C
illustrate one conventional method for depositing a conductive material in the cavities of a substrate (e.g., workpiece).
FIG. 1A
illustrates a cross sectional view of a substrate having various layers disposed thereon. This figure illustrates a silicon dioxide layer (SiO
2
)
2
(dielectric layer) having deposited thereon a barrier or adhesive layer
4
and a seed layer
6
.
The dielectric layer
2
is generally etched with cavities before the barrier layer
4
and the seed layer
6
are deposited thereon. The cavities in the dielectric layer
2
are generally etched using a reactive ion etching (RIE) method. The barrier layer
4
may be tantalum (Ta), titanium (Ti), tungsten (W), titanium-tungsten (TiW), titanium nitride (TiN), Nb, CuWP, CoWP, or other materials or combinations thereof that are commonly used in this field. The barrier layer
4
is generally deposited on the dielectric layer
2
using any of the various sputtering methods, chemical vapor deposition (CVD), electrodeposition or electrolyte/electroless plating method. Thereafter, the seed layer
6
is deposited over the barrier layer
4
. The seed layer
6
may be deposited on the barrier layer
4
again using various sputtering methods, CVD, or electroless deposition or combinations thereof. The seed layer
6
thickness, depending on the substrate topography, may vary from 20 to 4000 Å.
After depositing the seed layer
6
, a conductive material
8
(e.g., copper) is generally used to fill the cavities of the dielectric layer
2
. This is illustrated in FIG.
1
B. The conductive material
8
may be formed on the seed layer
6
by CVD, sputtering, electroless plating, electro-deposition, or combinations thereof. The conductive material
8
and the seed layer
6
are generally the same material. The cavities are typically overfilled with the conductive material
8
as shown.
Once the conductive material
8
is formed in the cavities of the substrate, the substrate is typically transferred to another equipment for polishing/planarizing the top surface of the substrate as illustrated in FIG.
1
C. Typically, the substrate is planarized using a conventional chemical mechanical polishing (CMP) device. The conductive material
8
overburden can be removed using a conventional CMP method. Portions of the seed layer
6
and the barrier layer
4
on the top surface of the substrate are also polished to electrically isolate the various structures. The remaining seed layer
6
in the cavities is embodied in the conductive material
8
as illustrated in FIG.
1
C.
Referring back to
FIGS. 1A-1B
, the depth
9
c
of the cavities in the dielectric layer
2
can range from 0.2 to 5 um for interconnects and up to 50 um or more for packages. When depositing the conductive material
8
over the substrate, it is desirable to overfill the cavities to, for example, 50 to 200% of the depth
9
c
in order to minimize defects in the wiring structure. For example, for the structure of
FIG. 1A
, assume that the depth
9
a
is about 0.5 um and the width
9
b
is about 10.0 um. Thus, the larger cavity includes the width
9
b
of 10.0 um and a total depth of about 1.0 um (measured from the bottom of the cavity to the top of the substrate). To completely fill the larger cavity, a minimum depth of at least 1.0 um of the conductive material
8
must be deposited therein. Further, an additional amount of the conductive material
8
is overfilled in the larger cavity to make certain that the cavity is completely filled and to minimize wiring defects. Thus, the additional amount (i.e., 50%) of the conductive material
8
over the larger cavity should be at a depth
9
e
of at least 0.5 um. In this case, when the depth
9
e
is about 0.5 um, the conductive material
8
formed over the field regions will be at a depth
9
d
of about 1.5 um. In other words, an overburden of at least 1.5 um of the conductive material
8
will be deposited over most of the field regions of the substrate while a smaller overburden of at least 0.5 um will be deposited over the larger cavities. Thus, the overburden of 0.5 to 1.5 um of the conductive material
8
will be deposited over the various features of the substrate.
The disparity of the conductive material
8
overburden across the substrate results in longer polishing time and higher costs using the conventional CMP process. Thus, there is a need for a deposition process that minimizes the amount of the conductive material
8
overburden across the substrate, as well as to minimize the disparity of the overburden depths on the surface of the substrate.
FIGS. 2A-2F
illustrate another conventional method for depositing a conductive material in the cavities of a substrate.
FIG. 2A
illustrates a dielectric (SiO
2
) layer
2
that is etched with cavities and having a barrier layer
4
and a seed layer
6
deposited thereon, similar to the structure of FIG.
1
A. Again, the cavities in the dielectric layer
2
are typically etched using an RIE method.
FIG. 2B
illustrates a photoresist material
12
coated on top of the seed layer
6
. Using a positive photoresist process, a mask (not shown) is used such that ultraviolet light is applied only to the photoresist material
12
that is formed in the cavities of the substrate. The photoresist that is exposed to the ultraviolet light (photoresist in the cavities) is degraded as the ultraviolet light breaks down the molecular structure of the photoresist. The degraded photoresist is then removed from the cavities of the substrate using an appropriate solvent or RIE method, resulting in the structure as illustrated in FIG.
2
C. Although a positive photoresist process is described herein, a negative photoresist process can also be used to form the structure of FIG.
2
C.
For substrates having large cavities of, for example, width
9
b
greater than 2 um, photoresist removal from the cavities may require additional steps. For example, the photoresist material
12
in the cavities may interact with the seed layer
6
such that using a solvent to remove the photoresist material
12
may be inadequate. In this case, after applying the solvent for photoresist dissolution, the substrate is exposed to oxygen plasmas in order to ash away/strip off the remaining photoresist material
12
from the seed layer
6
in the cavities of the substrate.
When exposing a copper seed layer to oxygen plasma, copper oxides, copper sulfides, or copper-oxide-sulfide compounds may be formed on the copper seed layer, particularly when the photoresist material contains sulfur-bearing elements. These compounds that are formed on the copper seed layer is generally resistive to a conductive material, and should be removed before any conductive material is deposited on the seed layer. Thus, a second stripping process may be required to remove the oxides, sulfides, or oxide-sulfides.
In many wiring structures having submicron features, the copper seed layer in

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